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301 results on '"A. Hatayama"'

1. Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion

Author

Sato, Keno, primary, Nakatani, Takayuki, additional, Ishida, Takashi, additional, Okamoto, Toshiyuki, additional, Ichikawa, Tamotsu, additional, Katayama, Shogo, additional, Iimori, Daiske, additional, Takagi, Misaki, additional, Zhao, Yujie, additional, Yamamoto, Shuhei, additional, Kuwana, Anna, additional, Katoh, Kentaroh, additional, Hatayama, Kazumi, additional, and Kobayashi, Haruo, additional

Published
2023
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2. A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation

Author

Katoh, Kentaroh, primary, Yamamoto, Shuhei, additional, Zhao, Zheming, additional, Zhao, Yujie, additional, Katayama, Shogo, additional, Kuwana, Anna, additional, Nakatani, Takayuki, additional, Hatayama, Kazumi, additional, Kobayashi, Haruo, additional, Sato, Keno, additional, Ishida, Takashi, additional, Okamoto, Toshiyuki, additional, and Ichikawa, Tamotsu, additional

Published
2023
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4. A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation

Author

Yamato, Yuta, Yoneda, Tomokazu, Hatayama, Kazumi, Inoue, Michiko, Yamato, Yuta, Yoneda, Tomokazu, Hatayama, Kazumi, and Inoue, Michiko

Abstract

In return for increased operating frequency and reduced supply voltage in nano-scale designs, their vulnerability to IR-drop-induced yield loss grew increasingly apparent. Therefore, it is necessary to consider delay increase effect due to IR-drop during at-speed scan testing. However, it consumes significant amounts of time for precise IR-drop analysis. This paper addresses this issue with a novel per-cell dynamic IR-drop estimation method. Instead of performing time-consuming IR-drop analysis for each pattern one by one, the proposed method uses global cycle average power profile for each pattern and dynamic IR-drop profiles for a few representative patterns, thus total computation time is effectively reduced. Experimental results on benchmark circuits demonstrate that the proposed method achieves both high accuracy and high time-efficiency., ITC : 2012 IEEE International Test Conference , 5-8 Nov. 2012 , Anaheim, CA, USA

Published
2023

7. High Precision Voltage Measurement System Utilizing Low-End ATE Resource and BOST

Author

Sato, Keno, primary, Nakatani, Takayuki, additional, Katayama, Shogo, additional, Iimori, Daisuke, additional, Ogihara, Gaku, additional, Ishida, Takashi, additional, Okamoto, Toshiyuki, additional, Ichikawa, Tamotsu, additional, Zhao, Yujie, additional, Katoh, Kentaroh, additional, Kuwana, Anna, additional, Hatayama, Kazumi, additional, and Kobayashi, Haruo, additional

Published
2022
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8. Evaluation of Code Selective Histogram Algorithm For ADC Linearity Test

Author

Zhao, Yujie, primary, Katoh, Kentaroh, additional, Kuwana, Anna, additional, Katayama, Shogo, additional, Iimori, Daisuke, additional, Ozawa, Yuki, additional, Nakatani, Takayuki, additional, Hatayama, Kazumi, additional, Kobayashi, Haruo, additional, Sato, Keno, additional, Ishida, Takashi, additional, Okamoto, Toshiyuki, additional, and Ichikawa, Tamotsu, additional

Published
2022
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9. Innovative Practices Track: Innovative Analog Circuit Testing Technologies

Author

Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel Barragan, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, and Tamotsu Ichikawa

Published
2022

10. Innovative Practices Track: Innovative Analog Circuit Testing Technologies

Author

Mangelsdorf, Chris, primary, Madhvaraj, Manasa, additional, Mir, Salvador, additional, Barragan, Manuel, additional, Iimori, Daisuke, additional, Nakatani, Takayuki, additional, Katayama, Shogo, additional, Ogihara, Gaku, additional, Zhao, Yujie, additional, Wei, Jianglin, additional, Kuwana, Anna, additional, Katoh, Kentaroh, additional, Hatayama, Kazumi, additional, Kobayashi, Haruo, additional, Sato, Keno, additional, Ishida, Takashi, additional, Okamoto, Toshiyuki, additional, and Ichikawa, Tamotsu, additional

Published
2022
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14. Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer

Author

Toshiyuki Okamoto, Daisuke Iimori, Takashi Ishida, Akemi Hatta, Jianglin Wei, Shogo Katayama, Haruo Kobayashi, Keno Sato, Kazumi Hatayama, Anna Kuwana, Gaku Ogihara, Takayuki Nakatani, Tamotsu Ichikawa, Minh Tri Tran, and Yujie Zhao

Subjects
business.industry, Computer science, law, Node (networking), Audio analyzer, Operational amplifier, business, Computer hardware, law.invention
Published
2021

15. AMR-Net: Convolutional Neural Networks for Multi-resolution Steady Flow Prediction

Author

Yasuhiro Idomura, Takashi Shimokawabe, Yuuichi Asahi, Sora Hatayama, Yuta Hasegawa, and Naoyuki Onodera

Subjects
Set (abstract data type), Flow (mathematics), Computer science, Computer cluster, Signed distance function, Translation (geometry), Convolutional neural network, Image resolution, Algorithm, Data modeling
Abstract

We develop a convolutional neural network model to predict multi-resolution steady flow data. Based on the image-to-image translation model pix2pixHD, our model can predict high resolution flow fields from the set of patched signed distance functions. By patching the high resolution data, our model uses roughly the one third of memory used by pix2pixHD. The accuracy of our model is almost the same as the U-Net model using the unpatched high resolution data.

Published
2021

16. Metallic Ratio Equivalent-Time Sampling: A Highly Efficient Waveform Acquisition Method

Author

Keno Sato, Yujie Zhao, Jianglin Wei, Shuhei Yamamoto, Anna Kuwana, Shogo Katayama, Yuto Sasaki, Toshiyuki Okamoto, Takashi Ishida, Takayuki Nakatani, Tri Minh Tran, Kazumi Hatayama, Haruo Kobayashi, and Tamotsu Ichikawa

Subjects
Signal generator, Sampling clock, Computer science, Electronic engineering, Sampling (statistics), Waveform, Device under test, Ic testing, Analog device, Time–frequency analysis
Abstract

In LSI testing, equivalent time sampling techniques are frequently used because the input signals to the device under test and the sampling clock are controllable; when the repetitive input signals are applied to the analog device under test, its output signals can be also repetitive. In this paper, we investigate an efficient waveform acquisition method with the equivalent-sampling using the metallic ratio of the sampling frequency and the input frequency, which is expected to be used for on-line, short-time and simple analog/RF/mixed-signal IC testing.

Published
2021

17. Input Signal and Sampling Frequencies Requirements for Efficient ADC Testing with Histogram Method

Author

Takashi Ishida, Shuhei Yamamoto, Yuto Sasaki, Jianglin Wei, Takayuki Nakatani, Keno Sato, Toshiyuki Okamoto, Haruo Kobayashi, Kazumi Hatayama, Anna Kuwana, Shogo Katayama, Tamotsu Ichikawa, Yujie Zhao, and Tri Minh Tran

Subjects
Sampling (signal processing), Silver ratio, Histogram, Range (statistics), Golden ratio, Signal, Root-mean-square deviation, Algorithm, Time–frequency analysis, Mathematics
Abstract

This article improves ADC sampling efficiency of the histogram method by investigating the ratio between the input saw frequency and the sampling frequency; the goal is to shorten ADC test time, and thus cost. Using a saw wave signal, the histogram RMS error within a certain range is simulated for the golden ratio, silver ratio, bronze ratio and prime number ratios. Golden ratio can halve the test time compared to the conventional method. We simulate an increase in output bins (the number of histogram bins), and find bronze ratio yields the best sampling efficiency.

Published
2021

18. Evaluation of High-Precision Nano-Ampere Current Measurement Method for Mass Production

Author

Ogihara, Gaku, primary, Nakatani, Takayuki, additional, Iimori, Daisuke, additional, Katayama, Shogo, additional, Kuwana, Anna, additional, Sato, Keno, additional, Ishida, Takashi, additional, Okamoto, Toshiyuki, additional, Ichikawa, Tamotsu, additional, Zhao, Yujie, additional, Wei, Jianglin, additional, Hatayama, Kazumi, additional, and Kobayashi, Haruo, additional

Published
2021
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19. High Precision Measurement of Sub-Nano Ampere Current in ATE Environment

Author

Sato, Keno, primary, Nakatani, Takayuki, additional, Ishida, Takashi, additional, Okamoto, Toshiyuki, additional, Ichikawa, Tamotsu, additional, Katayama, Shogo, additional, Ogihara, Gaku, additional, Iimori, Daisuke, additional, Zhao, Yujie, additional, Wei, Jianglin, additional, Kuwana, Anna, additional, Hatayama, Kazumi, additional, and Kobayashi, Haruo, additional

Published
2021
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21. Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies

Author

Sato, Keno, primary, Ishida, Takashi, additional, Okamoto, Toshiyuki, additional, Ichikawa, Tamotsu, additional, Wei, Jianglin, additional, Nakatani, Takayuki, additional, Zhao, Yujie, additional, Katayama, Shogo, additional, Yamamoto, Shuhei, additional, Kuwana, Anna, additional, Hatayama, Kazumi, additional, and Kobayashi, Haruo, additional

Published
2021
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22. Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer

Author

Iimori, Daisuke, primary, Nakatani, Takayuki, additional, Katayama, Shogo, additional, Ogihara, Gaku, additional, Hatta, Akemi, additional, Kuwana, Anna, additional, Sato, Keno, additional, Ishida, Takashi, additional, Okamoto, Toshiyuki, additional, Ichikawa, Tamotsu, additional, Wei, Jianglin, additional, Zhao, Yujie, additional, Tran, Tri Minh, additional, Hatayama, Kazumi, additional, and Kobayashi, Haruo, additional

Published
2021
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24. Metallic Ratio Equivalent-Time Sampling: A Highly Efficient Waveform Acquisition Method

Author

Yamamoto, Shuhei, primary, Sasaki, Yuto, additional, Zhao, Yujie, additional, Wei, Jianglin, additional, Kuwana, Anna, additional, Sato, Keno, additional, Ishida, Takashi, additional, Okamoto, Toshiyuki, additional, Ichikawa, Tamotsu, additional, Nakatani, Takayuki, additional, Tran, Tri Minh, additional, Katayama, Shogo, additional, Hatayama, Kazumi, additional, and Kobayashi, Haruo, additional

Published
2021
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25. Input Signal and Sampling Frequencies Requirements for Efficient ADC Testing with Histogram Method

Author

Zhao, Yujie, primary, Kuwana, Anna, additional, Yamamoto, Shuhei, additional, Sasaki, Yuto, additional, Kobayashi, Haruo, additional, Tran, Tri Minh, additional, Katayama, Shogo, additional, Wei, Jianglin, additional, Nakatani, Takayuki, additional, Hatayama, Kazumi, additional, Sato, Keno, additional, Ishida, Takashi, additional, Okamoto, Toshiyuki, additional, and Ichikawa, Tamotsu, additional

Published
2021
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26. Metallic Ratio Equivalent-Time Sampling and Application to TDC Linearity Calibration.

Author

Yamamoto, Shuhei, Sasaki, Yuto, Zhao, Yujie, Kuwana, Anna, Katoh, Kentaroh, Zhang, Zheming, Wei, Jianglin, Tran, Tri Minh, Katayama, Shogo, Sato, Keno, Ishida, Takashi, Okamoto, Toshiyuki, Ichikawa, Tamotsu, Nakatani, Takayuki, Hatayama, Kazumi, and Kobayashi, Haruo

Abstract

In LSI testing, equivalent time sampling techniques are frequently used because the input signals to the device under test and the sampling clock are controllable; when repetitive input signals are applied to the analog device under test, its output signals can be also repetitive. In this paper, we investigate an efficient waveform acquisition method with equivalent-sampling using the metallic ratio of the sampling frequency and the input frequency, which is expected to be used for on-line, short-time and simple analog/RF/mixed-signal IC testing. We reveal that metallic sampling technique can be a powerful tool for the TDC linearity calibration with the histogram method. [ABSTRACT FROM AUTHOR]

Published
2022
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27. Summing Node Test Method: Simultaneous Multiple AC Characteristics Testing of Multiple Operational Amplifiers

Author

Takashi Ishida, Riho Aoki, Anna Kuwana, Jianglin Wei, Takayuki Nakatani, Gaku Ogihara, Shogo Katayama, Jianlong Wang, Keno Sato, Toshiyuki Okamoto, Haruo Kobayashi, Akemi Hatta, Kazumi Hatayama, Tamotsu Ichikawa, and Yujie Zhao

Subjects
Analogue filter, Power supply rejection ratio, Open-loop gain, Total harmonic distortion, law, Computer science, Amplifier, Hardware_INTEGRATEDCIRCUITS, Operational amplifier, Electronic engineering, Node (circuits), Test method, law.invention
Abstract

This paper proposes a summing node test method for the operational amplifier and shows the followings: (i) It can be used for parallel testing of multiple AC characteristics (such as open loop gain (AOL), PSRR and CMRR) of one operational amplifier simultaneously with the equivalent accuracy but much faster compared to the NULL method. Also it can measure them even for multiple operational amplifiers at the same time. (ii) It can measure THD, SNR and THD+N of the operational amplifier with the comparable accuracy to the audio analyzer usage case, by applying proper analog filters. In other words, it can measure them with remarkable accuracy at very low cost. These have been verified with simulations and experiments. The proposed summing node test method uses an inverting operational amplifier under test and its negative input is amplified by an auxiliary non-inverting operational amplifier. The input and power supply voltages for the operational amplifier under test are modulated by AC signals with different frequencies. The auxiliary amplifier output is digitized after analog filtering and FFT is performed to the digitized data. This proposed method can reduce operational amplifier test time with good accuracy but without expensive instruments at mass production shipping, to meet the requirements for IoT and automotive as well as audio applications.

Published
2020

28. Accurate Testing of Precision Voltage Reference by DC-AC Conversion

Author

Takashi Ishida, Anna Kuwana, Takayuki Nakatani, Kazumi Hatayama, Keno Sato, Tamotsu Ichikawa, Haruo Kobayashi, and Toshiyuki Okamoto

Subjects
Accuracy and precision, Materials science, Noise measurement, Histogram, Acoustics, Fast Fourier transform, Repeatability, Spectrum analysis, Temperature measurement, Voltage reference
Abstract

This paper describes an accurate and fast testing technique for a precision voltage reference. Our proposed DC-AC conversion and FFT spectrum analysis method is applied and its experiment results show that measurement accuracy within ±100μV and measurement variation (repeatability) within ±10μV are feasible.

Published
2020

29. Analog/Mixed-Signal Circuit Testing Technologies in IoT Era

Author

Toshiyuki Okamoto, Haruo Kobayashi, Kazumi Hatayama, Tamotsu Ichikawa, Tran Minh Tri, Yujie Zhao, Anna Kuwana, Takashi Ishida, Shogo Katayama, Keno Sato, Takayuki Nakatani, Jianglin Wei, and Manato Hirai

Subjects
Signal processing, business.industry, Computer science, 020208 electrical & electronic engineering, Mixed-signal integrated circuit, 02 engineering and technology, 020202 computer hardware & architecture, Variety (cybernetics), law.invention, Reliability (semiconductor), Sampling (signal processing), law, Embedded system, 0202 electrical engineering, electronic engineering, information engineering, Operational amplifier, Systems design, Internet of Things, business
Abstract

This paper introduces our production testing research results for analog and mixed-signal SoC in IoT era, such as operational amplifier, ADC, sampling circuit, timing related testing technologies. Notice that production testing and measurement / characterization for ICs are similar but different, and this paper introduces the former. The analog / mixed-signal testing plays a very important role in achieving both reliability and low cost for IoT and automotive systems. It also is a big technological challenge because there is no general method, but it requires state-of-the-art combination and optimization of a wide variety of technologies including circuit and system design as well as signal processing, control and measurement algorithms. Their overview including future technology challenges is described.

Published
2020

30. Innovative Test Practices in Asia

Author

Smith Lai, Yukiya Miura, Takaaki Kato, Seiji Kajihara, Harry H. Chen, Masao Aso, Takeshi Iwasaki, Satoshi Matsunaga, Haruo Kobayashi, Yousuke Miyake, Gavin Hung, Kazumi Hatayama, and Haruji Futami

Subjects
Reduction (complexity), Measurement method, Computer science, business.industry, Automotive industry, Session (computer science), business, Internet of Things, Test (assessment), Reliability engineering, Power control
Abstract

The IP session highlights three innovative test practices in Asia, which include a testing solution for the millimeterwave (76- to 81- GHz) without expensive instruments, an on-chip delay measurement method for in-field test and a power control method of at-speed scan test for IR violation reduction. These would be useful for automotive and IoT application device testing.

Published
2020

31. A Capture-Safe Test Generation Scheme for At-Speed Scan Testing

Author

Dept. of CSE, Kyushu Institute of Technology, Iizuka 820-8502, Japan, Semiconductor Technology Academic Research Center, Yokohama 222-0033, Japan, Dept. of ECE, University of Wisconsin - Madison, Madison, WI 53706, USA, Wen, X., Miyase, K., Kajihara, S., Furukawa, H., Yamato, Y., Takashima, A., Noda, K., Ito, H., Hatayama, K., Aikyo, T., Saluja, K. K., Dept. of CSE, Kyushu Institute of Technology, Iizuka 820-8502, Japan, Semiconductor Technology Academic Research Center, Yokohama 222-0033, Japan, Dept. of ECE, University of Wisconsin - Madison, Madison, WI 53706, USA, Wen, X., Miyase, K., Kajihara, S., Furukawa, H., Yamato, Y., Takashima, A., Noda, K., Ito, H., Hatayama, K., Aikyo, T., and Saluja, K. K.

Abstract

type:Journal Article, Capture-safety, defined as the avoidance of any timing error due to unduly high launch switching activity in capture mode during at-speed scan testing, is critical for avoiding test- induced yield loss. Although point techniques are available for reducing capture IR-drop, there is a lack of complete capture-safe test generation flows. The paper addresses this problem by proposing a novel and practical capture-safe test generation scheme, featuring (1) reliable capture-safety checking and (2) effective capture-safety improvement by combining X-bit identification & X-filling with low launch- switching-activity test generation. This scheme is compatible with existing ATPG flows, and achieves capture-safety with no changes in the circuit-under-test or the clocking scheme., 2008 13th European Test Symposium, 25-29 May 2008, Verbania, Italy, source:DOI: 10.1109/ETS.2008.13

Published
2020

32. Sharing Information to Eliminate Support Irregularities and Omissions: - Cases from Disaster Information Supporters in Japan

Author

Michinori Hatayama, Hideaki Sone, Dai Sato, Yoichi Kayama, and Shoko Miyagawa

Subjects
010504 meteorology & atmospheric sciences, business.industry, Computer science, Pillar, Information needs, Information support, Public relations, 010502 geochemistry & geophysics, business, Disaster response, 01 natural sciences, Blank, 0105 earth and related environmental sciences
Abstract

We proposed a classification of the information needs in the phases of disaster and disaster support activities carried out by Japanese information volunteers. The classification denoted irregularities and omissions in information support activities with the blank cells in the classification tables. According to the result, we proposed some styles of information support that would fill the gaps, and strongly recommended the remote help works targeting other information supporters as a probable fourth pillar of Japanese disaster response system.

Published
2019

33. Summing Node Test Method: Simultaneous Multiple AC Characteristics Testing of Multiple Operational Amplifiers

Author

Ogihara, Gaku, primary, Nakatani, Takayuki, additional, Hatta, Akemi, additional, Sato, Keno, additional, Ishida, Takashi, additional, Okamoto, Toshiyuki, additional, Ichikawa, Tamotsu, additional, Kuwana, Anna, additional, Aoki, Riho, additional, Katayama, Shogo, additional, Wei, Jianglin, additional, Zhao, Yujie, additional, Wang, Jianlong, additional, Hatayama, Kazumi, additional, and Kobayashi, Haruo, additional

Published
2020
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35. Analog/Mixed-Signal Circuit Testing Technologies in IoT Era

Author

Kobayashi, Haruo, primary, Kuwana, Anna, additional, Wei, Jianglin, additional, Zhao, Yujie, additional, Katayama, Shogo, additional, Tri, Tran Minh, additional, Hirai, Manato, additional, Nakatani, Takayuki, additional, Hatayama, Kazumi, additional, Sato, Keno, additional, Ishida, Takashi, additional, Okamoto, Toshiyuki, additional, and Ichikawa, Tamotsu, additional

Published
2020
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37. Innovative Test Practices in Asia

Author

Iwasaki, Takeshi, primary, Aso, Masao, additional, Futami, Haruji, additional, Matsunaga, Satoshi, additional, Miyake, Yousuke, additional, Kato, Takaaki, additional, Kajihara, Seiji, additional, Miura, Yukiya, additional, Lai, Smith, additional, Hung, Gavin, additional, Chen, Harry H., additional, Kobayashi, Haruo, additional, and Hatayama, Kazumi, additional

Published
2020
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39. Evaluation of Null Method for Operational Amplifier Short-Time Testing

Author

Riho Aoki, Tamotsu Ichikawa, Toshiyuki Okamoto, Kosuke Machida, Keno Sato, Takashi Ishida, Anna Kuwana, Shogo Katayama, Jianlong Wang, Takayuki Nakatani, Kazumi Hatayama, Haruo Kobayashi, and Yuto Sasaki

Subjects
Production testing, Measure (data warehouse), Capacitor, Computer science, Control theory, law, Amplifier, Null (mathematics), Spice, Hardware_INTEGRATEDCIRCUITS, Operational amplifier, law.invention, Compensation (engineering)
Abstract

This paper investigates the NULL method to apply for the mass production testing of the operational amplifier. The NULL method is widely used to measure the operational amplifier characteristics accurately at the laboratory level, but it takes relatively a long measurement time. Then, we have examined the operation of the NULL method circuit with simulations where the SPICE model provided by the vendor is used for the amplifier under test. Some experiments have been also performed to confirm the agreements to the simulation results. We have found that the proper selection of the compensation capacitor values in the NULL method circuit can lead to short-time and stable testing, which would yield its applicability to the mass production testing.

Published
2019

40. Accurate and Fast Testing Technique of Operational Amplifier DC Offset Voltage in µV-Order by DC-AC Conversion

Author

Keno Sato, Anna Kuwana, Riho Aoki, Haruo Kobayashi, Toshiyuki Okamoto, Kosuke Machida, Yuto Sasaki, Kazumi Hatayama, Shogo Katayama, Takayuki Nakatani, Takashi Ishida, Tamotsu Ichikawa, and Jianlong Wang

Subjects
Chopper, Materials science, Input offset voltage, law, System of measurement, Fast Fourier transform, Electronic engineering, Operational amplifier, Linearity, Voltage, DC bias, law.invention
Abstract

This paper describes an accurate and fast testing technique for small DC offset voltage of a high precision operational amplifier. Chopper techniques for DC-AC conversion and FFT spectrum analysis are combined and then accurate DC voltage measurement on the order of µV can be achieved. We have also investigated thermo-electromotive force effects and their countermeasures. Their simulations and experiments with prototype measurement systems have been carried out, and the measurement linearity up to as low as 0.2 µV of the DC measurement voltage was confirmed. We have also investigated its extension to multi-channel realization for short testing time.

Published
2019

41. Innovative Test Practices in Japan

Author

Tamotsu Ichikawa, Keno Sato, Hirotaka Arai, Haruo Kobayashi, Anna Kuwana, Takashi Ishida, Toshiyuki Okamoto, Jianglin Wei, Takayuki Nakatani, Takahiko Shimizu, Nene Kushita, Kazumi Hatayama, Yuji Gendai, and Yusuke Asada

Subjects
Reduction (complexity), Resource (project management), Computer science, business.industry, Distortion, Automotive industry, Session (computer science), business, Internet of Things, Reliability engineering, Test (assessment), Parametric statistics
Abstract

The IP session highlights three innovative test practices in Japan, which include DC parametric test time reduction using digital controlled DC resource and deep reconsideration for ADC distortion testing as well as test time reduction of low sampling rate and high-resolution ADC linearity. These would be useful for automotive and IoT application device testing.

Published
2019

42. Analysis on Tsunami Evacuation Options with Agent-based Simulation in Tourist Area

Author

Michinori Hatayama, Takato Kosaka, and Aurora Hernandez Hernandeze

Subjects
Transport engineering, 021110 strategic, defence & security studies, Geographic information system, business.industry, 0211 other engineering and technologies, Residence, 02 engineering and technology, Simulation system, 010502 geochemistry & geophysics, business, 01 natural sciences, Tourism, 0105 earth and related environmental sciences
Abstract

Tsunami evacuation is the most important ways to reduce the casualty. An evacuation simulation is an effective tool to analyze the tsunami evacuation. This study targeted a mixed area of tourism and residence in Zihuatanejo, Mexico. An agent-based simulation system was developed and some evacuation measures were proposed and evaluated. In this study, the effect of two kinds of measures were denoted; 1) vertical evacuation to hotels in inundation area, 2) leading evacuation by local residents. Finally in the evacuation scenarios which was constructed as the combination of 1) and 2) one of the most effective destination of leading evacuees was proposed.

Published
2018

43. <tex>$0.63\ \mathrm{m}\Omega \text{cm}^{2}$</tex> / 1170 V 4H-SiC Super Junction V-Groove Trench MOSFET

Author

Y. Saito, T. Masuda, Shinsuke Harada, T. Hatayama, and T. Kumazawa

Subjects
010302 applied physics, Physics, Trench mosfet, Condensed matter physics, 0103 physical sciences, Doping, 02 engineering and technology, 021001 nanoscience & nanotechnology, 0210 nano-technology, 01 natural sciences, Omega, Junction area
Abstract

4H-SiC super junction, $0.63\ \mathrm{m}\Omega \text{cm}^{2}$ and 1170 V, V-groove trench MOSFETs (SJ-VMOSFET) were demonstrated. The specific on-resistance $(R_{\text{on},\text{sp}})$ of the SJ-VMOSFET is the lowest ever among all the reported SiC-MOSFETs with the blocking voltage $(B_{\mathrm{v}})$ over 600 V. Superior electrical properties were realized with the structural combination of the V-groove MOS channel and the charge balance at super junction area. The $R_{\text{on},\text{sp}}$ analysis of SJ-VMOSFET was carried out after mounted on a TO-268 5pin package having a Kelvin source terminal. The V-groove {033 8} channels could keep a high inversion mobility even in increasing doping concentration over $1\times 10^{18}$ cm−3. The excellent-static and -dynamic performances of SJ-VMOSFET were allowed to realize the ultra-low loss switching applications.

Published
2018

44. Innovative practices on test in Japan

Author

Haruo Kobayashi, Kazumi Hatayama, Koji Asami, Jun Matsushima, Yoichi Maeda, and Yoshiro Tamura

Subjects
Microcontroller, Power demand, business.industry, Computer science, Automotive industry, Session (computer science), business, Manufacturing engineering, Test (assessment)
Abstract

The IP session highlights three innovative practices in Asia, which include low cost testing of analog front-end circuits, evaluation of complex analog filter and power reduction of power-on self-test for automotive MCU.

Published
2018

46. Evaluation of Null Method for Operational Amplifier Short-Time Testing

Author

Aoki, Riho, primary, Sato, Keno, additional, Ishida, Takashi, additional, Okamoto, Toshiyuki, additional, Ichikawa, Tamotsu, additional, Katayama, Shogo, additional, Sasaki, Yuto, additional, Machida, Kosuke, additional, Nakatani, Takayuki, additional, Wang, Jianlong, additional, Kuwana, Anna, additional, Hatayama, Kazumi, additional, and Kobayashi, Haruo, additional

Published
2019
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47. Accurate and Fast Testing Technique of Operational Amplifier DC Offset Voltage in µV-Order by DC-AC Conversion

Author

Sasaki, Yuto, primary, Ichikawa, Tamotsu, additional, Kuwana, Anna, additional, Hatayama, Kazumi, additional, Kobayashi, Haruo, additional, Machida, Kosuke, additional, Aoki, Riho, additional, Katayama, Shogo, additional, Nakatani, Takayuki, additional, Wang, Jianlong, additional, Sato, Keno, additional, Ishida, Takashi, additional, and Okamoto, Toshiyuki, additional

Published
2019
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48. Innovative Test Practices in Japan

Author

Asada, Yusuke, primary, Shimizu, Takahiko, additional, Gendai, Yuji, additional, Sato, Keno, additional, Ishida, Takashi, additional, Okamoto, Toshiyuki, additional, Ichikawa, Tamotsu, additional, Wei, Jiang-Lin, additional, Kushita, Nene, additional, Arai, Hirotaka, additional, Kuwana, Anna, additional, Nakatani, Takayuki, additional, Hatayama, Kazumi, additional, and Kobayashi, Haruo, additional

Published
2019
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