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On-board reconfiguration of FPGAs on a spacecraft offers the important advantage of allowing the reuse of the same hardware component for different functionalities during a mission. To be able to benefit from these features, a solution to cope with the challenges of using SRAMbased FPGAs in a radiation environment is required, and at the same time it is desired that the FPGA reconfiguration takes place at high speed. The BRAVE NG-MEDIUM FPGA offers a solution for this problem, by combining being radiation-hardened by design and reconfiguration of the programmable logic via a high-speed communication protocol, namely SpaceWire. In this paper we compare the performance of SpaceWire with Joint Test Action Group (JTAG) for NG-MEDIUM reconfiguration, in terms of the time elapsed when uploading a bitstream file from a Central Processing Unit (in our case from a computer) to the Field Programmable Gate Array (FPGA) and the time needed for uploading such bitstream and configuring the FPGA with the uploaded bitstream.

Reliability is an important concern in many Field Programmable Gate Array (FPGA) based designs, mainly in applications which must be free of faults, and need to be available for long periods of time. Triple Modular Redundancy (TMR) is a well known approach for a system to tolerate possible faults, but a permanent fault in the TMR hardware may diminish the redundancy advantage. In this paper, we present a low cost solution to improve some dependability figures of a TMR system. The methodology comprises a design flow, which is used in the implementation of the proposed Partial Bit stream for Multiple Partitions (PB4MP) mechanism. The strategy allows modules's relocation in different Reconfigurable Partitions (RPs) using only one bit stream per module, enabling fault prevention and fault removal (recovery) actions. The results show that with a minor increase in the digital design configuration memory, it is possible to improve considerably the TMR availability, reliability and maintainability.

Although FPGA logic resources groups present some homogeneity, available Dynamic Partial Reconfiguration (DPR) tools consider them entirely heterogeneous. This assumption implies that each partial bit stream has to be allocated to one Reconfigurable Partition (RP). To solve this limitation, we present in this paper a new Assisted Design Flow (ADF) that implements a very efficient Partial Bit stream for Multiple Partitions (PB4MP) technique. Based on the Xilinx tools flow, the proposed ADF: takes advantage of the Xilinx tools constraints, does not require any intermediate manual steps, gives more freedom to the tools than similar approaches, and only repeats the regular flow once. Having the ability to disable all interface signals from each RP, this method allows to relocate modules safely in different RPs with the same bit stream or by an internal configuration memory swap, which increases system dependability and significantly facilitates the hardware tasks management.

The Triple Modular Redundancy (TMR) strategy is a common and good option for a system to recover from possible faults. However, in case of a permanent fault in the TMR hardware, the redundancy advantage can be destroyed. In this paper, we present a low cost solution to enable Fault Detection, Isolation and Recovery (FDIR) in a TMR system. Our methodology uses the Assisted Design Flow (ADF) that implements Partial Bitstream for Multiple Partitions (PB4MP). This method allows to relocate modules in different Reconfigurable Partitions (RPs) using only one bitstream per module. The results show that with a minor increase in the program memory of the digital design, it is possible to increase considerably the TMR availability.

Field Programmable Gate Arrays (FPGAs), as any other electronic devices, are designed according to some life expectancy figures. For this reason, its lifetime is finite given due to appearance of faults caused by the natural physical degradation. In this paper, we present a low cost solution for autonomous detection of faults at the end of FPGAs life cycle. Our proposed methodology starts from a pre-analysis of memory elements belonging to modules under verification. Then, with a proper organization, it is created a list of all memory elements, controlled through a Built-In Self-Test (BIST) implementation via the FPGAs Internal Configuration Access Port (ICAP). By means of this list, a virtual scan chain is created, where the vectors (test and result) are written and read using the FPGA reconfiguration capabilities, which means there is no extra hardware to create the physical scan chain. The detection algorithm is implemented in the available system processing unit. The results show that with a minor increase in the program memory of the digital design, it is possible to perform an offline hardware testing of each sub-module in the existing FPGA, with no need of stopping the remaining of the system.