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Future high luminosity colliders will require front-end electronics with unprecedented performance, both in space and time resolution (tens of micrometers and tens of picoseconds) and in radiation hardness (tens of megagray). Moreover, the high number of events will generate an enormous quantity of data (some terabits per second), and the limited bandwidth requires to perform data selection as close as possible to the front-end stage, to reduce the amount of data transmitted and stored for off-line analysis.The TimeSpOT (TIME and SPace real-time Operating Tracker) project, funded by INFN, is developing a complete demonstrator of a tracking device including all the features needed for future high luminosity experiments.In this presentation, we describe the first prototype of the readout electronics in 28 nm CMOS technology. The modules of the front-end circuitry have been designed and integrated in a test chip, which will allow us to characterize each block separately, and to connect them in a processing chain to evaluate the overall performance.

Historical monuments in the urban environment are affected by anthropic vibrations, therefore the health monitoring of those structures is mandatory. The frequency domain analysis is the standard procedure to infer the presence of damages, but usually it requires expensive equipment, time consuming elaborations, trained personnel. Moreover, especially if the monument to be investigated is a large building, many devices are necessary. In order to face all these difficulties, we propose the recently developed motion magnification methodology. It is based on a processing procedure that plays the role of a microscope for slight motions within a video. In recent years, experimental studies explored this methodology applied to simple geometries, demonstrating its potentialities and reliability thorough comparison with conventional and accurate vibration instruments, such as accelerometers and lasers. However, the study of large ancient monuments is lacking. Our case-study, the so-called Temple of Minerva Medica located between the railway tracks and a tramway in the center of Rome, intends to fill the gap.

The present paper illustrates the use of the transmissibility function H with several approaches and formulated in different ways to analyze ambient vibration measurements of an archeological building. The use of H as a consolidated estimator of the frequency response function (FRF) of the studied structure, can take advantage of its application also to other approaches, such as the horizontal-to-vertical spectral ratio (HVSR) approach. In fact, in the case of ancient masonry and ruined buildings, characterized by high heterogeneities and complexities, modal estimators computed from on-the-field data are typically quite noisy, so that accurate identification of the analyzed structure is sometimes challenging. Through a mutual validation of the results by several methods useful indications on the reliability of findings can be provided. To such purpose, also operational modal analysis (OMA) was performed and compared to modal identification by H function. A practical application to the so-called temple of Minerva Medica, located in Rome, was described.

This work concerns the design of a temperature sensor for multi-purpose pattern recognition applications designed in a 28 nm CMOS technology. The sensor resolution is 1°C between −40°C and 125°C. A vertical bipolar transistor is used as the sensing element generating the reference for the Analog-to-Digital Converter (ADC), based on a dual slope, Wilkinson architecture. An auto-compensation technique has been implemented in order to mitigate process variations, mainly dominated by the contributions of the current reference circuit.

This paper presents the characterization of an input/output interface circuit designed for multi-purpose pattern recognition applications compatible with low-voltage fully differential signaling (LVDS) standard. The driver and receiver circuits described in this work has been designed and fabricated in a 28 nm CMOS technology. The prototype chip has been mounted on a printed circuit board with physical characteristics similar to the real application case and fully validated up to 1 Gb/s with input random patterns.

This paper presents the design of a LVDS input/output interface circuit for the next generation of Associative Memory (AM) chip. The bandwidth of Associative Memories is a critical aspect that needs to be addressed in order to increase the number of comparisons per second. Our aim is to transfer parallel buses at 500 MHz. Since a large number of receivers/drivers will be included in the AM chip, power consumption of the circuits has been taken into account. The design discussed in this work has been submitted for fabrication in December 2016 in a 28 nm CMOS technology.

A first prototype of a readout ASIC in CMOS 65 nm for a pixel detector at High Luminosity LHC is described. The pixel cell area is 50×50 μm2 and the matrix consists of 64×64 pixels. The chip was designed to guarantee high efficiency at extreme data rates for very low signals and with low power consumption. Two different analogue front-end designs, one synchronous and one asynchronous, were implemented, both occupying an area of 35×35 μm2. ENC value is below 100 e− for an input capacitance of 50 fF and in-time threshold below 1000 e−. Leakage current compensation up to 50 nA with power consumption below 5 μW. A ToT technique is used to perform charge digitization with 5-bit precision using either a 40 MHz clock or a local Fast Oscillator up to 800 MHz. Internal 10-bit DAC's are used for biasing, while monitoring is provided by a 12-bit ADC. A novel digital architecture has been developed to ensure above 99.5% hit efficiency at pixel hit rates up to 3 GHz/cm2, trigger rates up to 1 MHz and trigger latency of 12.5 μs. The total power consumption per pixel is below 5 μW. Analogue dead-time is below 1%. Data are sent via a serializer connected to a CMOS-to-SLVS transmitter working at 320 MHz. All IP-blocks and front-ends used are silicon-proven and tested after exposure to ionizing radiation levels of 500-800 Mrad. The chip was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 and was submitted in July 2016 for production. Early test results for both front-ends regarding minimum threshold, auto-zeroing and low-noise performance are high encouraging and will be presented in this paper.

A front-end channel prototype for pixel detectors has been designed for the upgrades of the HL-LHC experiments. The circuit is based on a Krummenacher feedback network to continuously reset the charge sensitive amplifier and on a fast threshold discriminator to implement a time-over-threshold (ToT) method and perform amplitude measurement. The circuit was developed in a 65 nm CMOS technology and takes an overall area not exceeding 25 μm×50 μm. The power dissipation per channel, not including dynamic consumption, is around 5 μW. This paper is in particular concerned with the characterization of the charge sensitive amplifier, whose gain and recovery time can be adjusted to comply with changes in the experiment parameters. A very small gain dispersion was detected in the set of characterized samples. An equivalent noise charge of 120 electrons was found for a detector emulating capacitance of 100 fF. The response of the amplifier is compatible with the speed requirements for the foreseen application.