Search

This paper presents an encoding variation on the Crosstalk-Harnessed Signaling (CHS) technique, aimed towards eliminating the common-mode eigenvector included in the Hadamard matrix for CHS encoding/decoding. This is accomplished by either removing the eigenvector or making it differential by concatenating matrices in a diagonal fashion, or by adding columns to the matrix; this results in a non-square matrix that delivers a larger number of signals to be routed in the interface. Simulation results show the signaling/routing overhead translates in a significantly higher performance for high-speed parallel interfaces with very high routing integration levels.

This article analyzes the performance of the bias tee circuit in visible light communications. The response of a simple bias tee circuit is studied by modifying the inductor and capacitor values, and different LED colors. The results show the best capacitor and inductor commercial values that should be placed on the bias tee circuit in order to obtain the best frequency response from LEDs of different colors. All the analysis and results explained on this paper are entirely theoretical.

The growing architectural complexity of Unified Extensible Firmware Interface (UEFI) requires a functional validation during system testing which in turn is becoming more complex and time-consuming. Unfortunately, there are few available solutions specifically designed to address this issue. We have proposed a novel technique which can automatically generate Colored Petri Net (CPN) from the UEFI firmware source code and use CPN simulation to keep track of the UEFI execution step-by-step at run-time. The simulation can indicate where the execution departs from a normal path, which in turn helps validation engineers to quickly deduct the root cause of the problem. The implemented validation tool can be incorporated into the existing validation workflow and requires no additional hardware equipment. A case study on the functional validation of UEFI USB Bus driver of a commercial embedded platform is used to demonstrate the proposed validation technique.

In the last decades, skin cancer increased its incidence becoming a public health problem. Technological advances have allowed the development of applications that help the early detection of melanoma. In this context, an image processing was developed to obtain Asymmetry, Border, Color, and Diameter (ABCD of melanoma). Using neural networks to perform a classification of the different kinds of moles. As a result, this algorithm developed after an analysis of 200 images was obtained a performance of 97.51%.

We present an algorithm for generating Spice netlists with varied parameters/variables in order to support Monte Carlo simulations. A number of data structures are required to randomly or pseudo-randomly vary transistor parameters or simulation parameters/variables. This algorithm ensures that Spice sub-circuits and transistor fingers are expanded so that every transistor and transistor finger of the circuit is independently varied. Some versions of Spice do not have built-in support of Monte Carlo simulations. Therefore, this algorithm can enable engineers operating these Spice versions to generate netlists for executing Monte Carlo simulations. This is important since Monte Carlo simulations are commonly used to test the performance or operation of a circuit affected by parameter variations caused during the manufacturing process.

As Unified Extensible Firmware Interface (UEFI) architectural complexity increases to accommodate a growing number of requirements, UEFI functional validation is becoming a large complex and time-consuming task. We have implemented an integrated validation tool that uses Colored Petri Net (CPN) to model the UEFI execution behavior in real-time. This tool extends the existing validation workflow with a run-time CPN model simulation that can indicate the correctness of the firmware execution and potentially pinpoints the location of error. This in turn could help reduce debugging time. Functional validation of UEFI USB Bus driver on MinnowBoard MAX is used as an example to demonstrate the effectiveness of the proposed approach.

In this paper we present a novel scheme to perform firmware verification using a graphical Colored Petri Net (CPN). CPNs provide modeling features for concurrency, communication and synchronization as well as hierarchical abstraction and timing analysis. These features are used to perform firmware validation of the UEFI USB bus initialization. The CPN representation provides better visualization support to streamline the validation process. A Beagle Board is used to show the potential of the proposed firmware validation scheme.

We report a study of power supply reduction to near-threshold for an 8-transistor CNTFET SRAM cell. Voltage at near-threshold has an impact on delays, energy, energy-delay product, leakage current, and static noise margin. In addition, we have incorporated a removed metallic CNT approach to deal with non-semiconductor CNTs. In this study we investigate how to enhance SRAM performance by means of two techniques: Gated Power Supply and Word-line Boosting. Using the gated power supply technique, power saving is over 5X, while the average delay is increased by 3.5X as compared to 0.9V Vdd. On the other hand, word-line boosting technique (where Read and write word lines are boosted with additional 100mV) helps to improve write and read delays that are faster by 3.8X and 1.7X, respectively at Vdd=0.4V. Lowest Energy delay product (EDP) for gated power supply and word-line boosting is at 0.5V and 0.4V, respectively. EDP compared to nominal Vdd of 0.9V is lowered by 38% and 56.9% respectively for the mentioned techniques.

In this paper we report an in-depth study of power supply reduction towards near-threshold for an 8-transistor CNTFET SRAM cell. Near-threshold voltage provides savings in power consumption, but has negative impact on delays, noise margin and yield. We have incorporated a removed metallic CNT approach to deal with non-semiconductor CNTs. Monte Carlo simulations have shown that with Vdd down to 0.5V, 0.72% of the cells are non-functional after removing the metallic CNTs. The power saving is over 5X, while the average delay is increased by 3.5X as compared to 0.9V Vdd. To further improve yield and performance, the gated cell power supply technique is applied which weakens the pull-up transistors during write and effectively eliminates all the write failures at near-threshold voltage level. At Vdd=0.5V, the cell with gated power supply improves write performance and write EDP by 1.5X and 2.9X compared to the non-gated cell. It also saves 70% total energy and achieves 38% lower EDP than a cell at nominal Vdd (0.9V).

Autonomously configuring and self-healing a large-scale wireless sensor network requires a light-weight maintenance protocol that is scalable. Further, in a battery powered wireless sensor network duty-cycling a node's radio can reduce the power consumption of a device and extend the lifetime of a network. With duty-cycled nodes the power consumption of a node's radio depends on the amount of communication it must perform and by reducing the communication the power consumption can also be reduced. Multi-parent hierarchies can be used to reduce the communication cost when constructing a recursive area clustering hierarchy when compared to single-parent solutions that utilize inefficient communication methods such as flooding and information propagation via single-hop broadcasts. The multi-parent hierarchies remain scalable and provide a level of redundancy for the hierarchy.

In this study, we present a Carbon Nanotube (CNT) FET based 8T SRAM cell and its performance in near threshold voltage region. Metallic CNTs (M-CNTs) grow alongside semiconductor CNTs in current synthesis process, but they can be removed using novel techniques. This in turn creates open circuit and degrades the performance and functionality of SRAM cells. In this paper we apply a removed metallic CNT tolerant approach. The near threshold performance of the 8T SRAM cells with the tolerant approach is simulated and optimized to obtain best performance under the supply voltage from 0.4V to 0.9V. An evaluation of energy delay product and SNM shows a favorable tradeoff for the 0.6V power supply. The energy savings for cells with 0.6V power supply are 56.5% and 10.0% for average and worst case, respectively, compared with 0.9V; on the other hand, it has about 58% longer max delay and 25.8% lower static noise margin. The average and worst case values of EDP for 0.6V is 34.0% and 27.8% lower than that of 0.9V, with only 0.09% more invalid cell.

This article presents the methodology to reconstruct images of ship hulls in turbid waters from an information gathered to a system composed of video camera, laser line-point and sonar scanning, which were incorporated into an underwater vehicle that has a navigation control. The acquired data is processed by diffuse algorithms that have demonstrated low computational complexity and high efficiency in image reconstruction. We present the results of image reconstruction of ship hulls in low visibility conditions.

On behalf of the Organizing Committee, it is our pleasure to welcome you to Boise, Idaho, USA, and the 2012 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2012). The Midwest Symposium is the longest-running symposium sponsored by the IEEE Circuits and Systems Society. Throughout its history, it has provided a forum for researchers and educators to share their enthusiasm and results in the Circuits and Systems area. This year's Symposium focuses on the latest trends in circuits and systems research and the increasing impetus towards multi-disciplinary research. The Symposium features sessions on trends in developing nanoscale devices as well as in new technologies for circuits and systems.

A metallic CNT renders a short circuit between drain and source in a CNTFET. Technologies capable of removing metallic CNTs create open circuits which degrades SRAM cell performance and functionality. In this paper we present a design approach to tolerate removed metallic CNT in CNTFET SRAM. –x00D7; CNTs to form a CNTFET. An extremely high probability of having a functional memory array can be obtained with a modest semiconducting CNT probability (P semi ) of 90% and a 1×4 uncorrelated CNT array. Three optimization schemes are also proposed to minimize the impact of metallic CNT removal.

In this study we present 3T and 3T1D DRAM cells designed using FinFET technology. Overall, the 3T DRAM cell has a 43.6% faster write speed than the 3T1D cell and uses less dynamic current (30.4% less write current and 14.6% less read current). The FinFET 3T1D DRAM cell offers a 16.7% faster read speed and 48.6% less read leakage current than the 3T1D cell. The 3T DRAM cell offers less variation in delays, up to 37% less than the 3T1D cell for write delay, due to parameter corner simulations. Overall for a system, the 3T FinFET DRAM cell is more promising due to its low dynamic current and significantly shorter write speed which leads to a smaller maximum delay.

In this paper a novel modular superscalar execution core is presented for a medium grain reconfigurable hardware. The processor can be configured for varying path widths, reservation station depths, and reorder buffer sizes with minimal redesign effort. An analysis comparing the superscalar core with a five-stage execution core shows that a speedup of 2.073 can easily be achieved while increasing area by only 29%.

In this paper we present a performance-power study of three flip-flops using FinFET technology. First we tested the original designs with Monte Carlo variations, and then biased the back gate of the FinFETs. We report the following flip-flop delays: setup, clock to Q, and hold times. Setup and clock to Q times (called register delay) are in the pipeline stage critical path. Our study shows that the Low Delay (LDFF) flip-flop has the shortest register delay of 5.7ps. The flip-flop with the lowest power consumption is LPFF with 17.4 µW. Our simulations were performed using the University of Florida UFDG: Double-Gate MOSFET Model through the interface of Spice3f5 and Ngspice (ngspice3.ufdg-3.7) and a 32nm technology.

A study of an eight-transistor (8-T) SRAM cell and its implementation in carbon nanotube FET (CNTFET) technology is presented. CNTFETs have shown great potential as post-silicon CMOS technology due to their superior transport properties, improved current density and excellent robustness to process, voltage and temperature variations. HSPICE simulations demonstrate great advantages for this cell design over the traditional 6-T structure in terms of static power, dynamic power and noise margin. In current synthesis processes metallic CNTs are grown along with semiconductor CNTs, a metallic tolerant scheme is used to overcome the presence of metallic CNT. The reliability of a large-sized memory is also improved by having memory modules with spare columns.

In this paper a novel and extremely configurable execution core is presented for a standard five-stage pipelined processor. This processor implementation targets a medium grain highly reconfigurable hardware architecture that has been developed for DSPs applications. Using the Spec Espresso and Li benchmarks, analysis of different data forwarding mechanisms and machine per system clock factors are offered. Results show that with an increase in 16.7% or 28.7% hardware size execution time can be reduced by up to 10.79% and 15.63% respectively.

The underwater vehicle control has two problems to deal with; parametric uncertainty and unknown disturbance. Sliding Mode Control (SMC) effectively addresses these issues and is therefore a viable choice for controlling underwater vehicles. On the other hand, this method is known to be susceptible to chatter, which is a high frequency signal induced by the switching control. In this paper a new control methodology called Model-free High Order Sliding Modes Control (HOSMC) is introduced. HOSMC principal characteristic is that it keeps the main advantages of the standard SMC, removing the chattering effects, this advantage is achieved without model knowledge. Real time experiments in a 1 DOF (Degree Of Freedom) underwater system are conducted to show control effectiveness. Finally, a comparative study regarding PID control and conventional SMC is given.

In this paper the components required to implement a central processing unit (CPU) and its arithmetic logic unit (ALU) are presented using a novel medium grain reconfigurable hardware architecture. The CPU can be configured to match the application's requirements in terms of word-size, number and type of units, and instruction set. The MIPS instruction set has been used to show the potential of the processing unit. The clock for this implementation is calculated to be in the order of 2GHz for current technologies.

In this study we present a metallic carbon nanotube (CNT) tolerant CNTFET memory. The proposed scheme includes a number of uncorrelated (independent) CNTs in series to form CNTFETs provides tolerance to metallic CNTs. To increase driving capabilities parallel (correlated) transistors are used. In addition spare columns are used to increase the memory array yield. An extremely high probability of having a functional memory array can be obtained with a modest semiconductor CNT probability (P semi ) of 90% and four uncorrelated transistors in series. The probability of having a functional 16×16 memory array is 90.27%, 99.48%, 99.98% and 100% with 0, 1, 2, and 4 spare columns, respectively.

Implementations of SRAM cells in FinFET and carbon nanotube FET (CNTFET) technologies are presented in this paper. The International Technology Roadmap for Semiconductors has identified these technologies as likely candidates to replace bulk CMOS. Leakage current is one of the major contributors in the power consumption in SRAM arrays; FinFETs have been shown to greatly reduce leakage current. The FinFET memory cells are presented. These cells dissipate 0.49 µW of static power. The CNTFET memory requires 0.195 µW of static power. In current synthesis processes Metallic CNTs are grown along with semiconductor CNTs, a metallic tolerant scheme is used to overcome the presence of metallic CNT. This CNTFET memory with metallic tolerance dissipates 0.21 µW of static power.

This paper presents and evaluates six novel, low-power, FinFET-based design schemes of the conventional NOR address decoder. These schemes differ in front- and back-gate connections and input signal swing. Simulations of these schemes were performed using a 32nm FinFET technology model and the schemes' performance was evaluated in terms of dynamic current consumption, delay, and leakage current consumption. The Low-Power (LP) scheme, a scheme where the FinFETs' back gates are reverse-biased for lower-power operation, was used as the base scheme for comparisons. The Shorted-Gate (SG) High Precharge Swing scheme has a better performance tradeoff than the other presented schemes, including the LP scheme. While dynamic power is 10.9% to 11.9% more than the LP scheme, the SG-High Precharge Swing scheme is 48.1% to 59.9% faster and dissipates 93.0% to 99.7% less leakage power than the LP scheme. In addition, the SG-High Precharge Swing scheme requires less supporting hardware as it needs one less voltage level and one less voltage conversion buffer than the LP scheme.

In this paper three carbon nanotube FET based static memory cells are compared on read and write delays, energy consumption, and performance under diameter variation corners. The carbon nanotube FET is currently considered to be the possible “beyond CMOS” device due to its1-D transport properties that include low carrier scattering and ballistic transport. The memory cells are classified by their transistor count (6-, 7- and 8-transistor cell.) Under a nominal diameter of 1.51nm, the 8-T cell has the lowest delay and energy consumption of 3.7ps and 0.348fJ, respectively. Simulations with transistor diameter variations show that small n-type device diameters result in significantly slow read and write delays. The 8-transistor cell dissipates the least energy when the transistor diameters range from 1.369nm to 1.659nm.

System-on-chip (SoC) designs have different intellectual property (IP) blocks that operate on independent clocks and signals crossing the clock domains could experience errors. This paper details the effects of clock skew on data and clock signals at the interface logic of communicating SoC modules. The clocks under consideration have the same frequency but with phase angles that range from 0 - 360deg. A single buffer between communicating modules shows data transfer rates of 10.25 times 109 data samples per second serially when the sender and receiver clocks have no skew. Increasing the phase shift (skew) between the sender and receiver clocks degrades this transfer rate to 6.75 times 109 samples per second per channel. Adjusting the phase shift between the sender and receiver clocks to always be between 0deg and 135deg improves the performance, keeping the data transfer rates in the range of 9.50 times 109 to 10.25 times 109 samples per second per channel. It is also shown that the interface logic tolerates skew significantly better if multiple stages of the interface logic and data path FIFO buffers are used.

Traditional single disruption tolerant radiation hardened SRAM designs are vulnerable to failure when exposed to particle strikes that induce multiple node disruptions. Such events become likely when devices with small feature sizes are operated in highly radioactive environments. This paper analyzes the effectiveness of hardened by design techniques created with the intent to mitigate multiple node disruptions in 90 nm CMOS. From the results, it has been concluded that acceptable tolerance to multiple node disruptions in 90 nm can be achieved through a unique combination of hardened memory and layout design techniques with moderate and calculable levels of layout interleaving.

This paper presents and evaluates two novel address decoding schemes that use selective precharging, the sense-amp and the AND decoders, in comparison to the conventional NOR decoder. Simulations for all three designs are performed using 65 nm CMOS technology and the delays of all three decoders are set to 120 ps for a common base comparison. The most selective AND decoder performs best and dissipates between 0.17% and 43.17% (29.29% on average) and the selective Sense-Amp decoder dissipates between 28.81% and 48.33% (39.96% on average) of the energy dissipated by the nonselective conventional decoder.

This paper presents a hardware based cache scheme to detect misbehaving nodes in mobile ad hoc network. In this scheme, the hardware monitors the activities of the upper-layer software and reports the misbehavior of the software to other mobile nodes in the network. The hardware cache stores the identity information of recently received packets. The detection mechanism uses the cache to detect packet dropping and packet misrouting. The simulation results show that the cache scheme can detect nearly 100% misbehaving nodes with nearly 0% false positive in the packet dropping scenario. In the packet misrouting scenario, the detection has nearly 0% false positive and more than 90% detection rate. The detection result could be used by other nodes to protect the network.

As the next generation network begins to incorporate the Internet, telecommunication and TV services, it becomes one of the most critical infrastructures for our society. Routers construct the skeleton of the network. Their kernel, the structure and configuration (scheduler) of the fabric, dominates the networks' performance, scalability, reliability and cost. Based on previous research, we proposed an interleaved architecture of multistage switching fabrics, which will meet the requirements for next generation routers. In this paper, we first assess its performance with a theoretical model which complements our previous simulation results. Moreover, the interleaved fabrics show great tolerance against internal hardware failures. Based on these properties, we propose the architecture of RAIF (redundant array of independent fabrics) for next generation network, which could get better performance and fault tolerance as RAID.

To detect misbehavior on data and mitigate adverse effects, we propose and evaluate a MultipAth routing single path transmission (MARS) scheme. The MARS combines multipath routing, single path data transmission, and end-to-end feedback mechanism together to provide more comprehensive protection against misbehavior from individual or cooperating misbehaving nodes. The MARS scheme and its enhancement E- MARS are evaluated by means of simulation under various adverse scenarios. The simulation results show that the MARS and E-MARS schemes provide better network performance and considerable protection to data transmission than some DSR-based transmission systems at the expense of moderate overhead. Compared to the DSR-based schemes, the proposed schemes deliver up to 45% more data with 20% misbehaving nodes under individual misbehavior, and up to 28% more data with 40% misbehaving nodes under colluded misbehavior.

Two novel memory decoder designs for reducing energy consumption and delay are presented in this paper. These two decoding schemes are compared to the conventional NOR decoder. Fewer word lines are charged and discharged by the proposed schemes which leads to less energy dissipation. Energy, delay, and area calculations are provided for all three designs under analysis. The two novel decoder schemes range from dissipating 3.9% to 23.6% of the energy dissipated by the conventional decoder. The delays of these designs are 80.8% of the conventional decoder delay. Simulations of the three decoders are performed using a 90 nm CMOS technology.

We present a novel MBU-tolerant design, which utilizes layout-based interleaving and multiple-node disruption tolerant memory latches. This approach protects against grazing incidence particle strikes, which produce disruptions with the widest possible spatial separation. Advantages with respect to size, complexity, and MBU tolerance are realized when this approach is compared to existing solutions.

As the Internet grows exponentially, scalable high performance routers and switches on backbone are required to provide a large number of ports, higher throughput, lower delay latency and good reliability. At present, most of these routers and switches are implemented on single crossbar as the switched backplane fabric. But the complexity of the single crossbar is increased with O(N2 ) in terms of crosspoint number, which is unacceptable for scalability when N becomes large. A delta class self-routing multistage interconnection network with the complexity of O(Ntimeslog2N) has been widely used in the ATM switches. However, the reduction of the crosspoint number results in the serious internal blocking. To solve this problem, quite a few scalable methods have been proposed. One of them, more stages with recirculation architecture is used to reroute the deflected packets, which increase the latency a lot. In this paper, we first bring out the multiple-panel MIN switching fabrics with interleaved recirculation. We also show how to correctly choose the recirculation points to reroute the cells, compared with the wrong connections of former publication. From the simulation under different traffic patterns, this new interleaved architecture, which is insensitive to congestion, could achieve better performance than its counterpart of single panel fabric.

A mesochronous pipeline architecture is described in this paper. Significant performance gains are possible with mesochronous pipeline over conventional pipeline architecture. The clock period in conventional pipeline scheme is proportional to the maximum stage delay while in mesochronous pipelining it is proportional to the maximum delay difference, which means higher clock speeds are possible in the proposed scheme. Also, the clock distribution network is simple and load on it is less in mesochronous approach resulting in significant power savings. An 8/spl times/8-bit multiplier using carry-save adder technique has been implemented in conventional and mesochronous pipeline approach using TSMC 180 nm (drawn length 200 nm). The over all power dissipation in mesochronous approach is less than 50% of the power dissipation in conventional approach. In conventional approach, the power dissipation in clock network and pipeline registers is close to 80% of total power dissipation, while in mesochronous approach the logic dissipates more power.

The specific characteristics of mobile ad hoc networks (MANETs) make cooperation among all nodes and secure transmission important issues in its research. Misbehaving nodes with different intentions and capabilities would conduct various types of misbehavior in the networks. In this paper, we present and evaluate a scheme, in which multipath routing combined with feedback mechanism are used to tackle misbehaviors on data delivery formed by one or more misbehaving nodes in an ad hoc network. Data and control packets are transmitted through two node-disjoint paths. The source is notified of suspected misconduct of intermediate nodes through feedback mechanism. A simple derivation of this scheme is also discussed. The proposed scheme and the derivation are compared with the single path routing protocol DSR by means of simulation implemented at normal and adverse scenarios. The simulation results show that the proposed scheme and the derivation provide considerable protection in ad hoc networks at the expense of moderate overhead introduced by multipath routing. In a network with up to 40% misbehaving nodes, the proposed scheme and the derivation result in around 17% in data receive rate over the single path DSR

Reconfigurable hardware offers a number of advantages over custom integrated circuits, including low development cost, high flexibility, and high adaptability to changing requirements. However, this alternative does incur some reduction in performance, especially for computationally intensive tasks such as digital signal processing. Recent developments in both research and industry have aimed to reduce this gap. This paper introduces a novel reconfigurable architecture that pipelines computations at the bit level. The architecture includes a number of features to improve performance, including medium-grain cells, hierarchical interconnections, and minimal clocking overhead. Circuit simulations demonstrate that the basic cell runs at 1.5 GHz in a modest 180-nm technology. At this speed, we estimate that the device could compute a 256-point fast Fourier transform in 829 ns.

A mesochronous pipeline scheme is described in this paper. In a conventional pipeline scheme each pipeline stage operates on only one data set at a time. In the mesochronous scheme, pipeline stages operate on multiple data sets simultaneously. The clock period in conventional pipeline scheme is proportional to the maximum pipeline stage delay while in mesochronous pipelining, it is proportional to the maximum pipeline stage delay difference, which means higher clock speeds are possible and number of pipeline stages is significantly less. In mesochronous approach the clock distribution network is simple and load on it is less resulting in significant power savings. Also, the variations in supply current drawn by clock network is significantly less in mesochronous scheme, thus power supply noise (IR drop and Ldi/dt noise) is less. An 8times8-bit multiplier using carry-save adder technique has been implemented in conventional and mesochronous pipeline approach using TSMC 180 nm (drawn length 200 nm). The over all power dissipation in mesochronous approach is less than 50% of the power dissipation in conventional approach. In conventional approach, the power dissipation in clock network and pipeline registers is close to 80% of total power dissipation, while in mesochronous approach logic dissipates more power.

A novel design for decreasing energy and delay during the read cycle of a standard six-transistor differential SRAM cell is presented in this paper. Removal of the pre- charge transistors from the bit-lines of the SRAM reduces energy consumption. This also eliminates the need for a pre- charge phase which decreases the total delay of a read cycle. Additional logic to improve the speed of a read and to ensure that the bit-lines retain a sufficient voltage difference is placed just before the output on the bit-lines. This is especially significant in the design of pipelined memories where the delay per stage is determined by the time it takes to read a value from a cell as opposed to decoding an address or generating the output of the SRAM. Circuit simulations in 180-nm CMOS show a decline in energy consumption by a minimum of 9.2% and up to 98.6%. Worst case delay is reduced by 27.6%. The following paper explains the proposed read logic in detail, describes the techniques used for the analysis, and compares the results with the standard method for fast, low-power read accesses.

The majority of digital circuits/systems primarily use synchronous clocking methodology. With clock distribution networks dissipating ever more power and the wire delays expected to become dominant, there has been increased activity to provide alternative solutions. This paper explores some potential methods for reducing global interconnect delays and improving throughput between communicating modules. Analysis of the classical repeater insertion is performed and a wave-pipelined repeater insertion scheme that addresses some shortfalls of the classical repeater insertion is proposed. An extension of the wave-pipelined repeater insertion scheme is presented and results show that its data retention capability offers reliable communication between any number of computing elements. The design of the communication channel is based on the assumption that the computing elements employ synchronous clocking while the communication channels are driven by locally generated clocks. Locally generating clocks along the communication channel avoids the clock distribution complexities and offers an ability to stop and start data transfer along the channel without the need for elaborate clock gating circuitry. Furthermore, no additional clock cycles are required to flush the pipe in the event of stalls. The circuitry that generates local clocks increases area and power, but shows significant performance advantages, particularly in providing a seamless interface between communicating modules running at different clock frequencies. Simulation results of the distributed FIFO communication channel in a modest 180 nm technology show locally generated clocks running at 2.22GHz with the memory buffers placed 2 mm apart.

In this paper we present a novel shared buffer scheme for systems on chip applications that require an interconnection network. The proposed scheme is based on a dynamically allocated multi queue self-compacting buffer. Two virtual channels shared the same buffer space. This in turn takes advantage of the available space. The proposed scheme outperforms existing approaches. In addition the scheme has similar performance using only half of the buffer size used in other traditional implementations.

Clock skew and clock distribution are increasingly becoming a major design concern in synchronous pipelined systems. We present a novel high-speed hybrid wave-pipelined linear feedback shift register that manages clock skew by permitting the clock to travel with its associated data through the pipeline. The wave-pipelined clock has a skew 8.34 times lower than that of a buffered clock and is 1.2 times faster.

In this paper, a piecewise second order approximation method to compute the sigmoid function is proposed and evaluated. The scheme provides high performance and it is inexpensive to implement in terms of hardware. It requires one multiplication and two additions for the sigmoid computation. It provides better precision with an average error of 5.3*10/sup -3/ which is less than other existing second/third order approaches having the average errors of 6.4*10/sup -2/ and 7.8*10/sup -2/ respectively. Finally the proposed scheme can provide a 1.15-1.67 speedup over existing schemes.