Search

In this paper, a direct modulated Power Line Communication (PLC) technique is presented, which realizes the transmitter part by a switched-capacitor (SC) implementation. It is shown that in terms of energy, latency and costs, the presented transmission scheme is an improvement compared to state-of-the-art carrier based solutions. Two variants of the transmitter will be analyzed that use an unshielded twisted-pair (UTP) cable to connect the network nodes differentially, while the supply of the nodes is embedded simultaneously. These PLC approaches have been verified by a discrete component based demonstrator and by a transmitter test chip, fabricated in a 180nm HV-CMOS SOI technology.

In this paper a low-power, low-noise interface for Micro Electro-Mechanical System (MEMS) silicon microphones built in a 55 nm MOSFET technology is presented. The designed interface is made up by a pseudo-differential structure, based on two single-ended Super-Source-Followers with PMOS input device, to reduce Flicker noise contribution that would affect low frequency applications. The challenge of this design regards the implementation in 55 nm of high performance analog cells. The device performs output integrated noise in the [20 Hz 20 kHz] audio band of about-110 dBV(A), with a total power consumption of 270 µ W from a 1.5 V voltage supply. Acoustic Overload Point (AOP) reaches a mean value of 130 dBspl.

This paper presents a fully integrated 65nm CMOS Low-Dropout (LDO) voltage regulator for MEMS devices in the microphone field. The proposed LDO exploits a nested loop to generate the regulated voltage. The external loop generates a precise mathbf{V}_{mathbf{out}} and the internal loop gets a fast transient response by means of a Flipped Voltage Follower (FVF). To achieve a high Power Supply Rejection (PSR) a Tail compensated Error Amplifier (EA) was used. Powered by a {1.8mathrm{V}pm 10%} VDD, the LDO provides a 1.2V regulated voltage in the whole temperature range {[-40, 85]{circ}mathrm{C}} while consuming a quiescent current of 8.7uA (15. 7u W of nominal power consumption). It is capable of driving from 200uA to 800uA of static current load without affecting performance. The LDO occupies an active area of {0.0363text{mm}{{2}}} {(0.3text{mm x} 0.121text{mm})} including the 70pF on chip capacitor. This means that the LDO can be used in a System on a Chip (Soc) thanks to the absence of an off-chip capacitor. The simulation shows a PSR {< -70text{dB}} in the audio band ([20, 20k]Hz), a PSR peak below -10dB and a fast transient response of 148ns. Furthermore, Montecarlo and PVT simulations show the robustness of the circuit. Worst cases prove that the mathbf{V}_{mathbf{out}} value never exceeds {1.2mathrm{V}pm 5%} during DC and transient analysis. The overall mathbf{V}_{mathbf{out}} error is 0.3%.

This study presents the first in depth characterization of deep cryogenic electrical behavior of a commercial 16 nm CMOS FinFET technology. This technology is well suited for a broad range of applications, including quantum computing, quantum sensing, and quantum communications. Cryogenic DC measurements and physical parameters extraction were carried out on this commercial FinFET technology, operating at room temperature, i.e., 300 K, and down to 2.95 K for different device types and geometries. This represents the main step towards cryogenic compact modeling and optimization of three-dimensional CMOS structures for quantum computations.

This paper presents the sensitivity analysis of an extended-range, second-order Incremental ADC (IADC) to the non-idealities of the operational amplifiers (op-amps) used. Different configurations of the extended-range IADCs are compared in terms of required ENOB and op-amp specifications. In all the configurations, a flash ADC with varying resolution is used as extended-range ADC. The ADC clock frequency is considered in all cases equal to 80 MHz. From the analysis it turns out that, in order to achieve a given ENOB, the extended-range IADC requires a significantly lower number of clock cycles than a conventional IADC, but the requirements of the op-amps are much more stringent.

This work presents the design and experimental validation of a photoacoustic setup that emulates the acoustic signal generated by a 20 MeV proton beam by ionoacoustic effect. This system serves as a practical tool to experimentally test ionoacoustic detectors in a simple yet representative setup prior to performing beam tests at accelerator facilities. To emulate the ionoacoustic effect the hereby presented Proton Sound Detector Testbench (ProSD-TB) uses a 70 W peak power pulsed laser and a specifically designed target absorber. The experimental validation of the ProSD-TB shows that it is capable to emulate a 20 MeV proton beam ionoacoustic signal in terms of signal amplitude (few Pa at the sensor surface) and frequency (2 MHz). The time domain signal generated by the ProSD-TB is acquired by means of a 64-ch Proton Sound Detector composed by a multichannel acoustic sensor, a dedicated analog front-end and signal processing. The ProSD-TB is validated against a 20 MeV ionoacoustic signal both in time domain and by comparing the 20 MeV dose deposition profile to an acoustic image generated by the Proton Sound Detector.

This paper presents the design and the validation of a continuous-time 2nd-order analog filter with 40 MHz -3 dB cut-off frequency. The circuit synthesizes a pair of conjugated complex poles by leveraging the inductive behaviour of the source node of the folded branch of a differential amplifier. This circuital technique dominates noise power and harmonic distortion by a simple input MOS transistor pair of a differential stage, resulting in 7-nV/√Hz in-band Input Referred Noise power spectral density and 69 dB output Dynamic Range. Moreover, this solution enables the introduction of gain in the filter, relaxing gain, power, and bandwidth requirements of the following stages in cascade structure. A filter prototype is realized in 28 nm CMOS, consuming 309 µW from 1.1 V and performing -6 dBm in-band Input IP3 at 20 dB passband gain.

This paper presents a dual-mode, multi-bit, second-order oversampling ADC, which can be configured into Sigma-Delta (SD) mode or Incremental (I) mode for interfacing a single or multiple sensors in multi-sensor platforms for automotive applications. Implemented in a 130-nm CMOS technology, the proposed ADC uses only 0.4 µm devices and operates at 2.5-V supply in order to be connected to high-voltage sensors, at the cost of intrinsic lower efficiency. The device achieves a maximum SNDR of 63.0 dB and 56.4 dB in the two modes, respectively, with a bandwidth of 2.1 MHz. By reducing the bandwidth to 1.25 MHz in SD-mode a SNR of 73.2 dB is achieved. In both operating modes, the ADC is clocked at 80 MHz, consuming 2.6 mA.

The demand for low-cost integrated circuits for automotive applications is increasing, while their cost must remain low to maintain product competitiveness. In this scenario, to guarantee DC-DC Buck converters high-efficiency and low cost (in terms of external components) increasing switching frequency is mandatory. The main problems are inherent the parasitic inductances and the parasitic capacitance of power MOSFET. This paper deals with the main critical aspects of increasing such switching frequency and show how to replace the external Schottky diode with an integrated structure. The case of a highspeed monolithic integrated circuit to control a load current is here proposed. Proper design allows to achieve switching frequency up to 1MHz with 94.4% efficiency.

The demand for low-cost integrated circuits for automotive applications is increasing, while their cost must remain low to keep the product competitive. In this scenario, a high-speed monolithic integrated circuit to control a load current is here proposed. It is composed by a level shifter and a gate driver for a high power switch in a DC-DC Buck converter to be realized in a low cost technology. For chip area reduction, an n-channel vertical power transistor is chosen as power transistor. High switching frequency (up to 1MHz) can be used to reduce external components size. The device is optimized to achieve 94.4% efficiency. Implementation concept, schematic and layout will be shown.

This paper presents a 4th-order continuous-time analog filter, with 100 MHz pass-bandwidth, based on the Super-Source-Follower biquadratic cell. The device is designed in order to meet specification for the latest telecommunications standards (LTE and 5G) and to efficiently operate in 16 nm-FinFET technology, exploiting the higher transistor intrinsic gain and efficiency, compared to the CMOS planar counterpart. Nonetheless, this work improves the Source-Follower analog filters state-of-the-art introducing a fully-differential biquadratic cell. The filter achieves 15.1 dBm in-band IIP3 at 10 MHz & 11 MHz input tones, with $968\ \mu \mathrm{W}$ power consumption from a single 1V supply voltage. In-band integrated noise is $85.78\ \mu \mathrm{V}_{\mathrm{rms}}$ for an overall Figure-of-Merit of 162.8 dB (j−1) which outperforms analog filters state of the art.

In automotive industry, every electronic device is driven by power switches. Indeed, the energy source is the car battery and it cannot, for instance, limit the output maximum voltage level. Consequently it could be higher than that supported by the load. The DC/DC Buck converter acts by limiting the output variables, according with the load specifications thereby ensuring its correct operation. The overall circuit will be composed of a power stage, the basic DC/DC converter, and a control loop, to provide a target output current value. This paper presents a control algorithm derived from an improved Peak Current Mode Control. The proposed algorithm defined Variable off-Time Peak Current Mode Control (VoT-PCMC) allows to contemporarily control in a DC-DC converter the ripple and the average current values, leading to a reliable load driver. The algorithm operation is simulated and then tested on hardware using dSpace, a Rapid Control Prototyping set-up.

In recent car developments, the proliferation of Communication systems with several electronics nodes results in increased cost, complexity, and wire harness weight. Such nodes are usually connected by several wires, like a differential communication bus, power supply lines, and possibly addressing lines. In this paper, novel transmitter designs for reducing the amount of interconnects between the nodes are proposed, exploting communication on the power lines, occupying unused parts of the spectrum. Besides the cost-saving, such methods reduce the automotive harness complexity and lead to more flexible solutions, lowering the demand for raw material and consequently reduced emissions during the production process. However, this requires adding specific sections to apply communication to the power line in each IC devices controlling the nodes. In this paper, some 180nm HV-CMOS SOI transmitter solutions are proposed to operate a data rate of up to 2Mbps. Extended simulations in an automotive environment model validate and compare the proposals.

In audio applications such as Bluetooth and USB-C, where low power consumption and tight surface budget represent the greater constraints, continuous-time sigma-delta modulators (CTSDM) are the most interesting solution for data conversion. The main concern is their particular sensitivity to jitter which makes using specific countermeasures mandatory. Willing to use FIR-DAC single bit strategy to limit jitter impact, this paper wants to highlight the importance of a proper quantitative jitter analysis preliminary to design, which in prior works has always been made with approximations. To do so, a fourth order single-bit CTSDM clocked at 3.072MHz is also presented, showing that properly sizing the FIR-DAC with this method allow to reach the desired Dynamic Range (DR) of at least 100dB over 20kHz without taking certain kind of risks.

Custom integrated DC-DC converters are frequently used to power system-on-chip architectures for achieving high-quality voltage regulation at the best possible efficiency. However, high-level models of such converters are usually incompatible with analog simulators and require the designer to re-assemble the circuit in the final design environment to verify the design with real transistor models. This process is both time consuming and error-prone. This paper presents a library of parameterizable, high-level macro-models for DC-DC converters, consisting of custom Verilog-A modules and cells from the standard libraries. The macro-models are compatible with analog simulators and offer a significant amount of flexibility to the designer.