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This paper presents a two-stage small signal intermediate frequency amplifier for high-temperature communication systems. The proposed amplifier is implemented using in-house silicon carbide bipolar technology. Measurements show that the proposed amplifier can operate from room temperature up to 251 °C. At a center frequency of 54.6MHz, the amplifier has a gain of 22 dB at room temperature, which decreases gradually to 16 dB at 251 °C. Throughout the measured temperature range, it achieves an input and output return loss of less than -7and -11 dB, respectively. The amplifier has a 1-dB output compression point of about 1.4 dBm, which remains fairly constant with temperature. Each amplifier stage is biased with a collector current of 10 mA and a base--collector voltage of 3 V. Under the aforementioned biasing, the maximum power dissipation of the amplifier is 221 mW. [ABSTRACT FROM AUTHOR]

Experimental and modeling results are reported for high-performance strained-silicon heterojunction bipolar transistors (HBTs), comprising a tensile strained-Si emitter and a compressively strained Si0.7Ge0.3 base on top of a relaxed Si0.85Ge0.15 collector. By using a Si0.85Ge0.15 virtual substrate strain platform, it is possible to utilize a greater difference in energy band gaps between the base and the emitter without strain relaxation of the base layer. This leads to much higher gain, which can be traded off against lower base resistance. There is an improvement in the current gain β of 27x over a conventional silicon bipolar transistor and 11x over a conventional SiGe HBT, which were processed as reference devices. The gain improvement is largely attributed to the difference in energy band gap between the emitter and the base, but the conduction band offset between the base and the collector is also important for the collector current level. [ABSTRACT FROM AUTHOR]

Accurate physical modeling has been developed to describe the current gain of silicon carbide (SiC) power bipolar junction transistors (BJTs), and the results have been compared with measurements. Interface traps between SiC and SiO2 have been used to model the surface recombination by changing the trap profile, capture cross section, and concentration. The best agreement with measurement is obtained using one single energy level at 1 eV above the valence band, a capture cross section of 1 x 10-15 cm², and a trap concentration of 2 x 1012 cm-2. Simulations have been performed at different temperatures to validate the model and characterize the temperature behavior of SiC BJTs. An analysis of the carrier concentration at different collector currents has been performed in order to describe the mechanisms of the current gain fall-off at a high collector current both at room temperature and high temperatures. At room temperature, high injection in the base (which has a doping concentration of 3 x 1017 cm-3) and forward biasing of the base--collector junction occur simultaneously, causing an abrupt drop of the current gain. At higher temperatures, high injection in the base is alleviated by the higher ionization degree of the aluminum dopants, and then forward biasing of the base--collector junction is the acting mechanism for the current gain fall-off. Forward biasing of the base--collector junction can also explain the reduction of the knee current with increasing temperature by means of the negative temperature dependence of the mobility. [ABSTRACT FROM AUTHOR]

Bipolar junction transistors (BJTs) of 4H-SiC, with a low collector-emitter forward voltage drop VCE, have been fabricated without base contact implantation. A comparison of BJTs on the same wafer with and without base contact implantation shows less than 10% higher VCE for the BJTs without base contact implantation. Omitting the base contact implantation eliminates high concentrations of implantation-induced defects that act as recombination centers. This is advantageous because it allows a shorter distance Wp+ between the emitter edge and the base contact, without affecting the current gain when no base contact implantation is used. The BJTs without contact implantation show a constant current gain as Wp+ was reduced from 3 to 1 μm, whereas the gain decreased by 45% for the BJTs with base contact implantation for the same reduction of Wp+. A key to the successful fabrication of low-forward-voltage-drop SiC BJTs without base contact implantation is the formation of low-resistivity Ni/Ti/Al ohmic contacts to the base. The contact resistivity on the base region (NWA≈ 4 x 1017 cm-3) was measured with linear transmission line method structures to ρC = 1.9 x 10-3 Ωcm², whereas the contact resistivity with the base contact implantation was ρC = 1.3 x 10-4 Ωcm², both after rapid thermal processing annealing at 800 °C. [ABSTRACT FROM AUTHOR]

An experimental study is presented to compare two different schemes used to incorporate a high concentration of dopants at the silicide/silicon interface for NiSi and PtSi, i.e., dopant segregation, with the purpose of lowering the Schottky barrier height (SBH) of the contact systems. Specifically, the interfacial dopant is introduced either through silicidation-induced dopant segregation (SIDS) or by silicide as diffusion source (SADS). For the latter, a postimplantation drive-in anneal is needed. For both silicide systems, the dopant segregation gives rise to a predominant effect, leading to an effective SBH that is independent of the original SBHs of PtSi and NiSi, which differs by 0.2 eV. Scheme SIDS is relatively simple in processing, but the sili. cidation process is dopant-dependent, leading to local variations of suicide formation. Scheme SADS addresses the adverse effect of dopant on silicidation by separating silicidation from dopant incorporation. [ABSTRACT FROM AUTHOR]

This paper presents the first results and analysis of strained Si n-channel MOSFETs fabricated on thin SiGe virtual substrates. Significant improvements in electrical performance are demonstrated compared with Si control devices. The impact of SiGe device self-heating is compared for strained Si MOSFETs fabricated on thin and thick virtual substrates. This paper demonstrates that by using high-quality thin virtual substrates, the compromised performance enhancements commonly observed in short-gate-length MOSFETs and high-bias conditions due to self-heating in conventional thick virtual substrate devices are eradicated. The devices were fabricated with a 2.8-nm gate oxide and included NiSi to reduce the parasitic series resistance. The strained layers grown on the novel substrates comprising 20% Ge did not relax during fabrication. Good ON-state performance, OFF-state performance, and cross-wafer uniformity are demonstrated. The results show that thin virtual substrates have the potential to circumvent the major issues associated with conventional virtual substrate technology. A promising solution for realizing high-performance strained Si devices suitable for a wide range of applications is thus presented. [ABSTRACT FROM AUTHOR]

Low-frequency noise and hole mobility are studied in Si and SiGe surface channel pMOSFETs with various types of high-κ dielectric stacks (Al2O3, Al2O3/HfAlOx/Al2O3 and Al2O3/HfO2/Al2O3) and TiN as gate electrode material. Comparisons are made with poly-SiGe-gated pMOSFETs as well as poly-Si/SiO2/Si references. The choice of channel material (strained SiGe or Si), gate material (TiN or poly-SiGe), and high-κ material (Al2O3, HfO2, HfAlOx) is discussed in terms of mobility and low-frequency noise. A TiN gate in combination with a surface SiGe channel is advantageous both for enhanced mobility and low 1/ƒ noise. The dominant sources of carrier scattering are identified by analyzing the mobility measured at elevated temperatures. The 1/ƒ noise is studied from subthreshold to strong inversion conditions and at different substrate biases. The mobility fluctuation noise model and the number fluctuation noise model are both used to investigate the 1/ƒ-noise origin. [ABSTRACT FROM AUTHOR]

Self-heating in a 0.25 μm BiCMOS technology with different isolation structures, including shallow and deep trenches on bulk and silicon-on-insulator (SOI) substrates, is characterized experimentally. Thermal resistance values for single- and multi- finger emitter devices are extracted and compared to results obtained from two-dimensional, fully coupled electrothermal simulations. The difference in thermal resistance between the investigated isolation structures becomes more important for transistors with a small aspect ratio, i.e., short emitter length. The influence of thermal boundary conditions, including the substrate thermal resistance, the thermal resistance of the first metallization/via layer, and the simulation structure width is investigated. In the device with full dielectric isolation-deep polysilicon-filled trenches on an SO! substrate-accurate modeling of the heat flow in the metallization is found to be crucial. Furthermore, the simulated structure must be made wide enough to account for the large heat flow in the lateral direction. [ABSTRACT FROM AUTHOR]

Strained layer Si[sub0.7]Ge[sub0.3] pMOSFETs were fabricated and shown to exhibit enhanced hole mobility, up to 35% higher for a SiGe device with 3-nm-thick Si-cap, and lower 1/f noise compared to Si surface channel pMOSFETs. The 1/f noise in the investigated devices was dominated by mobility fluctuation noise and found to be lower in the SiGe devices. The source of the mobility fluctuations was determined by investigating the electric field dependence of the 1/f noise. It was found that the SiO[sub2]/Si interface roughness scattering plays an important role for the mobility fluctuation noise, although not dominating the effective mobility. The physical separation of the carriers from the SiO[sub2]/Si interface in the buried SiGe channel pMOSFETs resulted in lower SiO[sub2]/Si interface roughness scattering, which explains the reduction of 1/f noise in these devices. The 1/f noise mechanism was experimentally verified by studying 1/f noise in SiGe devices with various thickness of the Si-cap. A too large Si-cap thickness led to a deteriorated carrier confinement in the SiGe channel resulting in that considerable 1/f noise was generated in the parasitic current in the Si-cap. In our experiments, the SiGe devices with a Si-cap thickness in the middle of the interval 3-7 nm exhibited the lowest 1/f noise. [ABSTRACT FROM AUTHOR]

Radiation hardness is tested for 4H-SiC n-p-n bipolar junction transistors designed for 1200-V breakdown voltage by implanting MeV protons and carbon ions at different doses and energies. The current gain is found to be a very sensitive parameter, and a fluence as low as 1 x 107 cm-2 of 10 MeV 12C can be clearly detected in the forward-output characteristics, IC(VCE). At this low dose, no influence of ion radiation is seen in the open-collector characteristics, IB(VEB), or the reverse bias leakage and breakdown properties. Moreover, by annealing the implanted devices at 420 °C for 30 min, a complete recovery of the electrical characteristics is accomplished. [ABSTRACT FROM AUTHOR]

Implantation-free mesa-etched 4H-SiC PiN diodes with a near-ideal breakdown voltage of 4.3 kV (about 80% of the theoretical value) were fabricated, measured, and analyzed by device simulation and optical imaging measurements at break-down. The key step in achieving a high breakdown voltage is a controlled etching into the epitaxially grown p-doped anode layer to reach an optimum dopant dose of ∼1.2 x 1013 cm-2 in the junction termination extension (JTE). Electroluminescence revealed a localized avalanche breakdown that is in good agreement with device simulation. A comparison of diodes with single- and double-zone etched JTEs shows a higher breakdown voltage and a less sensitivity to varying processing conditions for diodes with a two-zone JTE [ABSTRACT FROM AUTHOR]

Schottky-barrier source/drain (SB-S/D) presents a promising solution to reducing parasitic resistance for device architectures such as fully depleted UTB, trigate, or FinFET. In this letter, a low-temperature process (⩽ 700 °C) with PtSi-based SID is examined for the fabrication of n-type UTB and trigate FETs on SOI substrate (tsi = 30 nm). Dopant segregation with As was used to achieve the n-type behavior at implantation doses of! . 1015 and 5. 1015 cm-2. Similar results were found for UTB devices with both doses, but trigate devices with the larger dose exhibited higher on currents and smaller process variation than their lower dose counterparts. [ABSTRACT FROM AUTHOR]

MOSFETs of both polarities with PtSi-based Schottky-barrier source/drain (S/D) have been fabricated in ultrathin-body Si-on-insulator. The PtSi is formed in the S/D regions without lateral suicide growth under the gate spacers. This design leads to a 30-nm underlap between the PtSi-Si contacts and the gate edges resulting in low drive currents. Despite the underlap, excellent performance is achieved for both types of MOSFETs with large drive currents and low leakage by means of dopant segregation through As and B implantation into the PtSi followed by drive-in annealing at low temperatures. [ABSTRACT FROM AUTHOR]

A novel SiGeC HBT process with a quasi-self-aligned emitter-base architecture and a fully nickel-silicided extrinsic base region has been developed. A very low total base resistance RB was achieved along with simultaneous NiSi formation on the polycrystalline emitter and collector regions. Uniform silicide formation was obtained across the wafer, and the resistivity of the Ni(SiGe:C) silicide layer was 24 µ&ohms; · cm. About 50-100 nm of lateral growth of silicide underneath the emitter pedestal was observed. DC and HF results with balanced fT/fMAX values of 41/42 GHz were demonstrated for 0.5 × 10 µm² transistors. [ABSTRACT FROM AUTHOR]

A correction is presented to a caption to a photograph of Hyung-Seok Lee published in the previous issue.