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This study simulates and compares symmetric and asymmetric MoS2 nanosheet transistor structures. The results show that the asymmetric MoS2 nanosheet transistor achieves higher current density and better gate control, and thus, this structure is optimized to meet the current density requirement for low-power applications in the International Roadmap for Devices and Systems (IRDS). Dielectric materials of Al2O3 and HfO2 are investigated, and equivalent oxide thicknesses ranging from 0.8 to 2 nm are analyzed. Transistors with Al2O3 as the dielectric exhibit better performance than those with HfO2 due to the lower level of remote phonon scattering. The gate length and underlap region are scaled down from 14 to 5 nm and from 7 to 1 nm, respectively, in an attempt to further enhance the ON-current. The substoichiometric metal oxide AlOx is used to induce more electrons in the undoped MoS2 channel. AlOx increases the ON-current with no gate control degradation. After optimization, the transistor demonstrates a subthreshold swing of 62.3 mV/dec, a drain-induced barrier lowering (DIBL) of 21.6 mV/dec, and a current density of $495 ~\mu \text{A}/\mu \text{m}$ with a supply voltage of 0.65 V. Compared with Si gate-all-around transistors, the MoS2 nanosheet transistor exhibits excellent gate control, good electrostatics, and comparable current density. [ABSTRACT FROM AUTHOR]

InGaZnO thin-film transistors (IGZO TFTs) adopting p-type Si with different doping concentrations as the gate electrodes are fabricated to study the effects of the electrical coupling between the gate electrode and the gate dielectric on the carrier mobility in the IGZO channel. In general, the carrier mobility is found to increase with increasing gate doping concentration because more holes in the gate electrode can screen/suppress the remote phonon scattering of the gate dielectric on the channel electrons (the screening effect). However, for certain gate doping concentrations, the carrier mobility surprisingly shows a decrease instead (the anti-screening effect). This has three implications: 1) like the free electrons in the n-Si gate electrode of OTFT, the holes in the p-Si gate electrode can oscillate about the dopant ions; 2) when the oscillation frequency is close/equal to the atomic vibration frequency of the high- ${k}$ gate dielectric, the resulting resonance between the gate electrode and the gate dielectric can enhance the atomic vibration of the latter to increase the remote phonon scattering on the channel carriers of the IGZO TFTs; and 3) the anti-screening effect could occur in any MOS-based devices. [ABSTRACT FROM AUTHOR]

The effects of the Si-substrate doping concentration on electrical characteristics of back-gate (BG) and top-gate (TG) MoS2 field-effect transistors (FETs) are investigated. The experimental results show that MoS2 FETs fabricated on different-concentration Si substrates using the same processing have similar interface characteristics and surface roughness of gate dielectric but exhibit different carrier mobility, and the higher the doping concentration, the higher the carrier mobility. This is because the carriers in Si substrate can screen the phonon scattering from the low-energy surface optical phonon produced by the soft Hf-O bonds in HfO2 dielectric, which will couple with the carriers in MoS2 channel, resulting in the reduction of the mobility, and the higher the Si-substrate concentration, the better the screening effect. Also, it is found that the BG dielectric scattering will impact on the mobility of the TG transistor, which causes a similar change trend of carrier mobility to that of the BG MoS2 FET as the Si-substrate concentration increases. Therefore, it can be revealed that the Si-substrate concentration has an important influence on the carrier mobility of MoS2 FETs, and the high Si-substrate concentration is beneficial for fabricating high-performance BG and TG MoS2 FETs. [ABSTRACT FROM AUTHOR]

In this article, we report the temperature-dependent transistor characteristic of Epi-Gd2O3/AlGaN/GaN metal oxide semiconductor high electron mobility transistor (MOSHEMT) and compare its properties with that of AlGaN/GaN metal-Schottky high electron mobility transistor (HEMT) grown on 150 mm Si (111) substrate. Introducing an epitaxial single crystalline Gd2O3 between the metal gate and AlGaN barrier not only improves the gate leakage current significantly but also enhances its thermal stability. We observe that there is no significant change in the gate leakage current even at 473 K compared to that measured at room temperature (RT) (298 K), and this is also evident in the transistor’s subthreshold behavior at 473 K. We have determined the electric field within the Gd2O3 as well as AlGaN and investigated the leakage conduction mechanism through Gd2O3. The ION/IOFF of the transistor was measured as high as ~108 even at 473 K with the lowest VTH shift (91.4 mV) with temperature. Our measurements also confirm the presence of polar optical phonon scattering, which directly affects the 2-D electron gas (2DEG) mobility at high temperatures and thus the electrical characteristics of HEMT and MOSHEMT. [ABSTRACT FROM AUTHOR]

We report the characterization of the channel mobility properties of metal-oxide-semiconductor field-effect transistors (MOSFETs) on the heterogeneous β-Ga2O3-on-SiC (GaOSiC) substrate fabricated by an ion-cutting process. The mobility of GaOSiC MOSFETs is significantly improved as the postannealing temperature of Ga2O3 channel increases from 900 °C to 1200 °C. The GaOSiC transistor annealed at 1200 °C exhibits mobility consistent with the β-Ga2O3 donor wafer, which suggests that the defects in Ga2O3 channel induced by the H+ implantation for the ion-cutting step can be eliminated by the high-temperature annealing. As the ambient temperature (Tamb) increases from 0 °C to 150 °C, the mobility within the accumulation regime of GaOSiC MOSFETs decreases with the temperature following a Tamb−1 law, which is limited by the phonon scattering. The results of this work will be critically important for designing the transport properties of the GaOSiC channel, significantly advancing the development of Ga2O3 power devices on high thermal conductivity substrate. [ABSTRACT FROM AUTHOR]

With the development of separation and sorting techniques, highly enriched semiconducting single-walled carbon nanotubes (SWNTs) have become widely accessible, which has led to the rapid growth of high-performance solution-processed SWNT-based thin-film field-effect transistors (TFTs) showing capabilities comparable to the ideal single-SWNT FETs. With such improvements, theoretical studies and detailed analyses of these networks have become necessary. In this work, a model justifying the near-ideal electrical transport in SWNT networks is presented. The field-dependent resistive properties of the networks are calculated using a numerical solver based on the derived individual resistances of SWNTs and the intertube couplings. The model is capable of simulating mixed SWNT networks consisting of both metallic and semiconducting nanotubes of varying chiralities. Our analysis reveals that the high electrical currents in networks could be largely attributed to the suppression of phonon scattering and strong intertube couplings in highly dense SWNT networks (>30–40 SWNTs μm2). Comparisons between the simulated and experimental results indicate good agreement thereby demonstrating the accuracy of the proposed model. [ABSTRACT FROM AUTHOR]

This article reports that Hetero-interfacial-thermal resistance (HITR) due to phonon scattering and weak electron–phonon coupling at hetero-interfaces, can impact stacked Si gate-all-around (GAA) nanosheet field effect transistor (NSHFET) self-heating effect (SHE) and reliability. We have investigated the HITR of Si/SiO2 and Si/metal-silicides on SHE of vertically stacked Si GAA NSHFET. Our simulation predictions reveal that a very noticeable effect of the HITR of Si/M0 at front end of line (FEOL) and back end of line (BEOL) interface (FEOL/BEOL) is that the hot-spot location is shifted into the channel away from drain depletion region, which affects the device SHE and degrades device performance. The impact of nanosheet width (WNSH) and sheets stacking number (N) on device SHE and drive current degradation with and without HITR effect are also studied. It is revealed that wider nanosheets with lower HITR can be a better device design choice for heat mitigation in high performance logic transistors. [ABSTRACT FROM AUTHOR]

This article presents a comprehensive analysis of the characteristics of an n-type monolayer MoS2 piezoelectric field-effect transistor (PZFET) based on a realistic model that includes scattering by intrinsic phonons, remote phonons, and charged impurities. By employing the density-functional theory (DFT), first, we evaluated the effect of the uniaxial compressive out-of-plane strain on the band structure and carrier’s effective masses of a MoS2 monolayer. Thereafter, by solving the linearized Boltzmann transport equation (BTE), the carrier mobility, mean free path, and mean-free-time modulation under different vertical strains in the presence of various scattering mechanisms are computed. By the use of the computed properties, we assessed the characteristics of the PZFET, in which the vertical strain is induced in the monolayer MoS2 channel from the piezoelectric layer (π-layer). The results indicate that the studied PZFET in relation to both the ballistic and nonballistic transports is subthermionic [subthreshold swing (SS) smaller than 60 mV/decade] with a relatively large ION/IOFF ratio. The results based on the realistic model indicate that a monolayer MoS2 PZFET enables the scaling of the channel length and the supply voltage beyond the conventional field-effect transistors (FETs). [ABSTRACT FROM AUTHOR]

Amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with HfLaO as high-k gate dielectric have been fabricated, and p-type silicon wafers with resistivities of 0.001 ~ 0.002, 0.005, 0.02 ~ 0.021 and $5\sim 10\Omega \cdot $ cm are used as their gate electrodes. The carrier mobility of the samples show an increase with increasing gate acceptor concentration, indicating that the TFT performances are affected by the hole concentration in the gate electrode. The HfLaO gate dielectric is highly polarizable and so produces surface-optical phonons, which can scatter the electrons in the IGZO channel to reduce their mobility. Therefore, this work directly demonstrates that the holes in the gate electrode can have a screening effect to suppress this remote phonon scattering of the gate dielectric on the channel carriers, just like the electrons in the metal gate, ITO gate and n-silicon gate of field-effect transistors. [ABSTRACT FROM AUTHOR]

We study the noncoherent transport due to electron–phonon (e-ph) interaction in graphene nanoribbon (GNR) field-effect transistors (GNRFETs) using nonequilibrium Green’s function method in mode space. Phonon dispersion calculations in conjunction with the e-ph interaction computations show that in an armchair GNR, only a small number of phonon modes are coupled to the carriers. Our simulation shows that under a threshold gate voltage, the drain–source current is diminished by the low-energy phonons such as acoustic phonon modes and radial-breathing-like phonon modes, while at great biases of the gate, the current drop is essentially due to high-energy optical phonon modes. The effect of drain voltage on scattering process is discussed, which shows that at higher drain voltages, the ballisticity decreases. We also explore the phonon scattering dependence on the dimensions of GNRFET channel. In larger width ribbon, the impact of phonon scattering decreases. The channel with a length of 30 nm is ballistic up to 90%, and only when its length is increased to approximately 180 nm, transport becomes semiballistic, which infers to an effective mean free path of ~200 nm. [ABSTRACT FROM AUTHOR]

Electron transport in Si double-gate junctionless transistors (JLTs) is simulated on the basis of the multisubband Monte Carlo method, considering acoustic phonons, intervalley phonons, ionized impurities (IIs), and surface roughness (SR) scattering. It is demonstrated that JLTs can actually minimize the mobility degradation caused by SR scattering and improve the current drivability. On the other hand, II scattering is confirmed to degrade the current drivability compared with conventional MOSFETs with an intrinsic channel. However, the performance degradation in JLTs due to II scattering is shown to be insignificant, owing to the screening effect of free carriers and the forward scattering properties of high-speed carriers. Furthermore, by extracting a backscattering coefficient, the screening effect and the forward scattering properties are shown to more mitigate II scattering as the gate voltage increases. [ABSTRACT FROM AUTHOR]

The effects of self-heating on graphene transistor characteristics are examined by self-consistently solving the coupled nonequilibrium Green's function transport equation with the thermal transport equation. The results indicate that the substrate and gate insulator have significant effects on the temperature rise, decrease of on-current, and lowering of transconductance through surface polar phonon scattering, which causes self-heating effects. For graphene transistors with the channel length of a few hundred nanometers, the temperature rise of about 110 K and on-current lowering of about 17% are predicted because of self-heating. This indicates the importance of a coupled electro–thermal simulation for predicting graphene device characteristics and of thermal engineering on device performance. The dependence of the self-heating effects on the transistor channel length and phonon energy are also examined. [ABSTRACT FROM AUTHOR]

HEMT performance critically depends on contact resistance, particularly in cryogenic applications, where the semiconductor resistance contributions are reduced, thanks to lower optical phonon scattering rates. The literature offers little about the temperature dependence of contact resistances in HEMTs. We report a temperature-dependent comparison of the annealed and nonannealed ohmic contacts for low-noise InP HEMTs. Contact resistances of annealed Ge/Au/Ni/Au and nonannealed Ti/Pt/Au ohmic contacts were characterized as a function of temperature between 5 and 350 K. Side-by-side comparison exposes the differences of nonannealed versus annealed structures with respect to the contact and sheet resistance. Whereas both contact types show equivalent performances at cryogenic temperatures for recessed cap structures reminiscent of practical HEMTs, our annealed contacts display a significant increase in contact resistance with increasing temperature, in marked contrast to the near temperature independence found in our nonannealed contacts. The finding is of importance since the source resistance directly enters the transistor minimum noise figure F\min in field-effect transistors. Additional contributions to the parasitic sheet resistance of ohmic, overlay, and electroplated interconnect metals are also characterized as a function of temperature. [ABSTRACT FROM PUBLISHER]

In this paper, we review and extend recent work on the effect of random discrete dopants on the statistical variability in gate-all-around silicon nanowire transistors. The electron transport is described using the nonequilibrium Green's function formalism. Full 3-D real-space and coupled-mode-space representations are used. Two different cross sections (i.e., \2.2 \times \2.2 and \4.2 \times \4.2\ \nm^2) and two different channel lengths (i.e., 6 and 12 nm) have been considered. The resistivity associated with discrete dopants can be estimated from the averaged current–voltage characteristics. The threshold-voltage variability and the subthreshold-slope variability are reduced greatly in the transistors with longer channel length. Both are smaller at equivalent channel lengths in the \2.2 \times \2.2\ \nm^2 device due to better electrostatic integrity. At the same time, the on-state-current variability associated with the varying resistance of the access regions is virtually independent of the channel length. However, it is reduced greatly in the \4.2 \times \4.2\ \nm^2 transistor due to a fourfold increase in the number of dopants in the access regions and corresponding self-averaging effects. Finally, we present results for the smallest transistor combining two sources of variability (i.e., discrete random dopants and surface roughness) and phonon scattering. [ABSTRACT FROM PUBLISHER]

We study the effect of surface roughness (SR) at the \Si/SiO2 interfaces on transport properties of quasi 1-D and 2-D silicon nanodevices by comparing the electrical performances of nanowire (NW) and double-gate (DG) field-effect transistors. We address a full-quantum analysis based on the 3-D self-consistent solution of the Poisson–Schrödinger equation within the coupled mode-space nonequilibrium Green function (NEGF) formalism. The influence of SR scattering is also compared with phonon (PH) scattering addressed in the self-consistent Born approximation. We analyze transfer characteristics, current spectra, density of states, and low-field mobility of devices with different lateral size, showing that the dimensionality of the quasi 1-D and 2-D structures induces significant differences only for thin silicon thicknesses. Thin NWs are found more sensitive to the SR-induced variability of the threshold voltage with respect to the DG planar transistors. [ABSTRACT FROM PUBLISHER]

This paper presents an extension of a ballistic compact model to the case of nonballistic transport for the conventional carbon nanotube FET featuring a MOSFET-like operation. A large part of the novelty lies on the analytical implementation of acoustic phonon (AP) and optical phonon (OP) scattering mechanism. To carry out this implementation, some simplifications of the theoretical description are proposed while staying as close as possible to physics and keeping the high-speed simulation and good convergence capability of the compact model. The compact model simulation results are systematically compared and validated with respect to nonequilibrium Green function simulation results. Then, we have investigated the impact of AP and OP scattering on transistor figures of merit. Taking into account the scattering processes is of utmost importance for both analog and digital circuit designs, since neglecting the scattering leads to an overestimation of more than 70% of the main figures of merit and will mislead designers when optimizing the operating point for analog applications. [ABSTRACT FROM AUTHOR]

We present a detailed treatment of dissipative quantum transport in carbon-nanotube field-effect transistors (CNTFETs) using the nonequilibrium Green's function formalism. The effect of phonon scattering on the device characteristics of CNTFETs is explored using extensive numerical simulation. Both intra- and intervalley scattering mediated by acoustic (AP), optical (OP), and radial-breathing-mode (RBM) phonons are treated. Realistic phonon dispersion calculations are performed using force-constant methods, and electron-phonon coupling is determined through microscopic theory. Specific simulation results are presented for (16,0), (19,0), and (22,0) zigzag CNTFETs, which are in the experimentally useful diameter range. We find that the effect of phonon scattering on device performance has a distinct bias dependence. Up to moderate gate biases, the influence of high-energy OP scattering is suppressed, and the device current is reduced due to elastic backscattering by AP and low-energy RBM phonons. At large gate biases, the current degradation is mainly due to high-energy OP scattering. The influence of both AP and high-energy OP scattering is reduced for larger diameter tubes. The effect of RBM mode, however, is nearly independent of the diameter for the tubes studied here. [ABSTRACT FROM AUTHOR]

In this paper, we have extensively investigated the silicon thickness dependence of the low field electron mobility in ultrathin silicon-on-insulator (UT-SOI) MOSFETs operated both in single- and in double-gate mode. A physically based model including all the scattering mechanisms that are known to be most relevant in bulk MOSFETs has been extended and applied to SOI structures. A systematic comparison with the measurements shows that the experimental mobility dependence on the silicon thickness (T[subSI]) cannot be quantitatively explained within the transport picture that seems adequate for bulk transistors. In an attempt to improve the agreement with the experiments, we have critically rediscussed our model for the phonon scattering and developed a model for the scattering induced by the T[subSI] fluctuations. Our results suggest that the importance of the surface optical (SO) phonons could be significantly enhanced in UT-SOI MOSFETs with respect to bulk transistors. Furthermore, both the SO phonon and the T[subSI] fluctuation scattering are remarkably enhanced with reducing T[subSI], so that they could help explain the experimental mobility behavior. [ABSTRACT FROM AUTHOR]

A model based on optical phonon scattering is developed to explain peculiarities in the current drive, transconductance, and high-speed behavior of short-gate-length GaN transistors. The model is able to resolve these peculiarities and provides a simple way to explain transistor behavior in any semiconductor material system in which electron–optical-phonon scattering is strong. [ABSTRACT FROM PUBLISHER]