Search

A compact interlinking converter modular (ICM) for hybrid ac/dc microgrids with a distributed storage (DS) bus for storage integration is proposed in this article. The advanced ICM for hybrid ac/dc/ds microgrids involves the nine-switch topology with compact configuration and decreased number of active operating switches, which structurally equivalents to afford a dc interconnection port for dc subgrid, an ac interconnection port for ac subgrid, a ds interconnection port for ds subgrid, and two dc–dc converters for the interconnection ports for parallel DSs. In addition to the popular advantage of component elements saving, the suggested ICM, aggregating various interlinking converter cells (ICCs) into an ICM, is also proficient of participating computations from all ICC sensors to enhance the overall modular performance without building extra communication connection links between ICCs. With this in mind, a decentralized power management control strategy is realized by employing a coordination power control methodology to systematically handle various distributed generations (DGs), DSs, and ICM in a decentralized manner with improved communication fault ride-through capability. The controller hardware-in-the-loop experiments on a real-time digital simulator platform validates the achievement of the advanced ICM application in hybrid ac/dc/ds microgrids and the effectiveness of the associated decentralized power management scheme. [ABSTRACT FROM AUTHOR]

In this article, a novel bidirectional dc–dc converter (BDC) consisting of an active switched-inductor (A-SL) cell, a zero current ripple cell and an auxiliary capacitor cell is proposed for the battery energy storage system. The proposed BDC integrates with the advantages of high voltage conversion ratio, low power switch voltage stresses, zero ripple current on the low voltage side (LVS), and constant potential difference between the grounds of LVS and high voltage side. Thanks to the use of synchronous rectification technology, the efficiency of the proposed BDC is increased. The operating principles, the characteristics analysis and the parameter design of the proposed BDC are given. In addition, to show the merits of the proposed BDC, a comparison study involves the proposed converter and other BDCs is demonstrated. Finally, some experimental results obtained using a 1000 W prototype are presented to valid the effectiveness of the proposed BDC. 96.43% and 96.67% maximum conversion efficiencies can be achieved in the step-up and step-down modes, respectively. [ABSTRACT FROM AUTHOR]

Data center networks demand high-performance, robust, and practical data plane load balancing protocols. Despite progress, existing work falls short of meeting these requirements. We design, analyze, and evaluate Luopan, a novel sampling based load balancing protocol that overcomes these challenges. Luopan operates at flowcell granularity similar to Presto. It periodically samples a few paths for each destination switch and directs flowcells to the least congested one. By being congestion-aware, Luopan improves flow completion time (FCT), and is more robust to topological asymmetries compared to Presto. The sampling approach simplifies the protocol and makes it much more scalable for implementation in large-scale networks compared to existing congestion-aware schemes. We provide analysis to show that Luopan's periodic sampling has the same asymptotic behavior as instantaneous sampling: taking 2 random samples provides exponential improvements over 1 sample. We conduct comprehensive packet-level simulations with production workloads. The results show that Luopan consistently outperforms state-of-the-art schemes in large-scale topologies. Compared to Presto, Luopan with 2 samples improves the 99.9%ile FCT of mice flows by up to 35 percent, and average FCT of medium and elephant flows by up to 30 percent. Luopan also performs significantly better than Local Sampling with large asymmetry. [ABSTRACT FROM AUTHOR]

The traditional finite-control-set model predictive control (FCS-MPC) method for a cascaded H-bridge (CHB) rectifier has two main issues: heavy computational burden and low steady-state current performance. In this paper, a novel FCS-MPC method has been proposed for a single-phase CHB rectifier. The proposed method solves the optimization problem of FCS-MPC for one cell by one cell, like a “pipeline.” In the proposed method, the sampling period is divided into equal intervals by the number of cells. At the beginning of the first interval, the first cell selects its switching state to be applied. Then, the following cell selects its switching state to be applied at the beginning of next interval. Finally, the selected switching state of last cell will be applied at the beginning of the last interval. A cost function presenting the control objectives of common source current error and itself dc-link voltage error is evaluated for each cell. A single-phase three-cell CHB rectifier controlled by a DSpace DS1104 is tested and the experimental results show that a significant reduction in computational time, an improved steady-state current performance, and a comparable dynamic response are achieved in the proposed method in comparison with the traditional FCS-MPC method. [ABSTRACT FROM AUTHOR]

Data center networks often use multi-rooted Clos topologies to provide a large number of equal cost paths between two hosts. Thus, load balancing traffic among the paths is important for high performance and low latency. However, it is well known that ECMP—the de facto load balancing scheme—performs poorly in data center networks. The main culprit of ECMP’s problems is its congestion agnostic nature, which fundamentally limits its ability to deal with network dynamics. We propose Expeditus, a novel distributed congestion-aware load balancing protocol for general 3-tier Clos networks. The complex 3-tier Clos topologies present significant scalability challenges that make a simple per-path feedback approach infeasible. Expeditus addresses the challenges by using simple local information collection, where a switch only monitors its egress and ingress link loads. It further employs a novel two-stage path selection mechanism to aggregate relevant information across switches and make path selection decisions. Testbed evaluation on Emulab and large-scale ns-3 simulations demonstrate that, Expeditus outperforms ECMP by up to 45% in tail flow completion times (FCT) for mice flows, and by up to 38% in mean FCT for elephant flows in 3-tier Clos networks. [ABSTRACT FROM PUBLISHER]

This paper proposes a multiple-input versatile matrix converter (VMC) for integrating hybrid ac/dc energy resources and storages to the power grid. The VMC is developed from the traditional indirect matrix converter but operates in the reverse-boost mode rather than in the forward-buck mode. The reverse-boost mode is more relevant here since most renewable sources and energy storages have lower voltages than the grid. The eventual VMC developed uses an alternative nine-switch converter, rather than usual six-switch voltage-source converter, for providing six input terminals in total. One three-phase ac source and three dc sources, or other source combinations, can therefore be connected to the VMC. Powers from these sources are channeled to the three-phase utility grid through the VMC's current-source inverter. Their proper dispatches are guaranteed by the proposed control and modulation schemes, which also help maintain near-sinusoidal input and output current waveforms. Mathematical proofs, simulation, and experimental results have shown that the VMC can indeed operate as intended. [ABSTRACT FROM PUBLISHER]

This paper presents a novel matrix converter with one ac input and two ac outputs. The presented topology is based on the traditional indirect matrix converter, but with its rear-end six-switch inverter replaced by a compact nine-switch inverter. With only three extra switches added, the proposed converter can produce two sets of three-phase ac outputs, whose amplitudes, frequencies, and phases can appropriately be regulated. Features such as sinusoidal input and outputs, unity input power factor and minimum commutation count are all retained by the proposed topology, despite having an additional output. Its modulation is realized by the computationally less intensive carrier-based method, whose unique carrier requirements can easily be managed within a programmable logic device. Mathematical proof for validating sinusoidal input and outputs achieved by this modulation technique is also discussed, before being verified in simulation and experimentally, together with other findings. [ABSTRACT FROM AUTHOR]