Search

J-PARC E16 is an experiment to examine the origin of hadron mass through a systematic measurement of spectral changes of vector mesons in nuclei. The measurement of $e^{+}e^{-}$ pairs from the decay of vector mesons will provide the information of the partial restoration of the chiral symmetry in a normal nuclear density. To resolve a pulse pile-up and achieve good discrimination of $e^{+}$ and $e^{-}$ from the background of a reaction rate of an order of 10 MHz, the data acquisition (DAQ) system uses waveform sampling chips of APV25 and DRS4. The trigger rate and data rate are expected to be 1 kHz and 120–330 MiB/s, respectively. The DAQ system for readout of APV25 and DRS4 were developed, where events were synchronized by common trigger and tag data. The first commissioning in beam, called Run-0a, was performed in June 2020 with about 1/4 of the designed setup. The DAQ worked with a trigger rate of 300 Hz in the Run-0a and the main bottleneck was a large data size of APV25. Further optimization of the DAQ system will improve the performance. [ABSTRACT FROM AUTHOR]

The COherent Muon to Electron Transition (COMET) experiment aims to search for the neutrinoless muon to electron transition process with new sensitivity levels. The online trigger system is an integral part of achieving the sensitivity levels required and will be subject to an expected neutron fluence of up to $10^{12}\,\,n \cdot \mathrm {cm}^{-2}$ within regions inside the detector solenoid. Consequently, a significant number of soft errors in the logic of the onboard field programmable gate arrays (FPGAs) can occur, requiring error correction for single event upsets and firmware reprogramming schemes for unrecoverable soft errors. We studied the radiation tolerance of the COMET Phase-I front-end trigger system, called COMET TRIgger (COTTRI), subject to neutron fluence on order $10^{12}\,\,n \cdot \mathrm {cm}^{-2}$ with multiple error correcting codes and automatic firmware reconfiguration. The regions measured were the configuration random access memory (RAM), block RAM (BRAM) and also in a multigigabit transfer link using copper cables that will be used for communication between different trigger boards during Phase-I. The resulting cross sections observed suggest the most significant impact to the experiment will come from unrecoverable soft errors in configuration RAM (CRAM), with dead time expected to be 4.2% ± 1.3%. The effect of multibit errors in BRAM was found to be almost negligible in COMET Phase-I. In addition, multiple solutions have already been proposed in order to suppress these errors further. Soft errors observed in the multigigabit transfer links were measured to be of two orders of magnitude less impact compared to the unrecoverable errors in CRAM. We concluded that the COTTRI system meets the trigger requirement in COMET Phase-I. [ABSTRACT FROM AUTHOR]

A new Muon-to-Central-Trigger Processor Interface (MUCTPI) was built as part of the upgrade of the ATLAS Level-1 trigger system for the next Run of the Large Hadron Collider at CERN. The MUCTPI has 208 high-speed optical serial links for receiving muon candidates from the muon trigger detectors. Three high-end field-programmable gate arrays (FPGAs) are used for real-time processing of the muon candidates, for sending trigger information to other parts of the trigger system, and for sending summary information to the data acquisition and monitoring system. A System-on-Chip (SoC) is used for the control, configuration, and monitoring of the hardware and the operation of the MUCTPI. The SoC consists of an FPGA part and a processor system (PS). The FPGA part provides communication with the processing FPGAs, while the PS runs software for communication with the run-control system of the ATLAS experiment. In this article, we will describe our experience with running CentOS Linux on the SoC. Cross-compilation together with the existing framework for building the ATLAS trigger and data acquisition (TDAQ) software is being used in order to allow the deployment of the TDAQ software directly on the SoC. [ABSTRACT FROM AUTHOR]

A field programmable gate array (FPGA)-based online trigger system has been developed for the COherent Muon To Electron Transition (COMET) Phase-I experiment, which searches for muon-to-electron conversion as a signature of New Physics beyond the Standard Model. A drift chamber and trigger counters are devised to detect a mono-energetic electron from the conversion process in a 1-T solenoidal magnetic field. A highly intense muon source enables reaching unprecedented experimental sensitivity, however, it also generates undesirable background particles which increase the trigger rate to a much higher level than the capability of the data acquisition (DAQ) system. By using hit information from the drift chamber in addition to the trigger counter, the newly proposed online trigger system efficiently suppresses the background trigger rate while keeping the signal-event acceptance large. A characteristic of this system is the utilization of machine learning (ML) techniques for optimizing lookup tables (LUTs) implemented in hardware. Simulation studies show that the signal-event acceptance of the online trigger is 96% while the background trigger rate is reduced from 91 to 13 kHz. The global trigger system and trigger electronics that construct a distributed trigger architecture were built. The total trigger latency was estimated to be $3.2~\mathrm {\mu s}$. The trigger system test was carried out by using a part of the drift-chamber readout region. [ABSTRACT FROM AUTHOR]

The Belle II experiment at the SuperKEKB collider at KEK, Tsukuba, Japan has successfully started taking data with the full detector in March 2019. Belle II is a luminosity frontier experiment of the new generation to search for physics beyond the Standard Model of elementary particles, from precision measurements of a huge number of $B$ and charm mesons and tau leptons. To read out the events at a high rate from the seven subdetectors of Belle II, we adopt a highly unified readout system, including a unified trigger-timing distribution system (TTD), a unified high-speed data link system (Belle2link), and a common backend system to receive Belle2link data. Each subdetector frontend readout system has a field-programmable gate array (FPGA) in which unified firmware components of the TTD receiver and Belle2link transmitter are embedded. The system is designed for data taking at a trigger rate up to 30 kHz with a dead-time fraction of about 1% in the frontend readout system. The trigger rate is still much lower than our design. However, the background level is already high because of the initial vacuum condition and other accelerator parameters, and it is the most limiting factor of the accelerator and detector operation. Hence, the occupancy and radiation effects to the frontend electronics are rather severe, and they cause various kinds of instabilities. We present the performance of the system, including the achieved trigger rate, dead-time fraction, and stability, and discuss the experience gained during the operation. [ABSTRACT FROM AUTHOR]

The large Hadron collider (LHC) is expected to increase its center-of-mass energy from 13 to 14 TeV for Run 3 scheduled from 2022 to 2024. After Run 3, upgrades for the high-luminosity-LHC (HL-LHC) program are planned and the operation will start in 2027, increasing the instantaneous luminosity to 5.0–7.5 times its nominal luminosity. Continuous upgrades of the ATLAS trigger system are planned to cope with the high event rate and to keep the physics acceptance. During the long shutdown period before Run 3, new detectors will be installed to improve the trigger performance. A new trigger logic, combining information from detectors located outside of the magnetic field and new detectors installed inside the magnetic field, will be introduced for Run 3 to reduce the trigger rate. In order to handle data from the various detectors, a new trigger processor board has been developed and the design is presented. During the upgrade for HL-LHC, the trigger and readout systems of the first level hardware-based part are planned to be upgraded. Full-granularity information will be transferred to the trigger processor board which enables more OFF-line like track reconstruction in the hardware-based system. To handle the full-granularity information and perform the hardware-based track reconstruction, the trigger processor board will be equipped with a field programmable gate array (FPGA) with hundreds of transceivers and a large memory. Expected performance for the hardware-based endcap muon trigger in Run 3 and HL-LHC will also be presented. [ABSTRACT FROM AUTHOR]

The Mu3e experiment aims to find or exclude the lepton flavor violating decay μ+ → e+e−e+$ with a sensitivity of one in 1016 muon decays. The first phase of the experiment is currently under construction at the Paul Scherrer Institute (PSI, Switzerland), where beams with up to 108 muons per second are available. The detector will consist of an ultra-thin pixel tracker made from High-Voltage Monolithic Active Pixel Sensors (HV-MAPS), complemented by scintillating tiles and fibers for precise timing measurements. The experiment produces about 100Gbit/s of zero-suppressed data, which are transported to a filter farm using a network of field programmable gate arrays (FPGAs) and fast optical links. On the filter farm, tracks and three-particle vertices are reconstructed using highly parallel algorithms running on graphics processing units, leading to a reduction of the data to 100 Mbyte/s for mass storage and offline analysis. This article introduces the system design and hardware implementation of the Mu3e data acquisition and filter farm. [ABSTRACT FROM AUTHOR]

The design and performance of a new front-end acquisition system is presented in this paper. It was developed to be used with muon array with resistive plate chamber (RPCs) for tagging air showers (MARTA’s) RPC detectors that measure the muonic component of cosmic ray air showers. The system is hybrid and capable of counting active channels and performing a charge measurement. It is low power (1.43 W per 64 channels), compact ($21.6 \times 14.4\,\,\mathrm {cm^{2}}$ per 64 channels), stable, and reliable to comply with the strict demands of field operation associated with experiments that measure air showers. The front-end is based on an application-specified integrated circuit [Multi Anode Read-Out Chip (MAROC)] with 64 input channels, which is responsible for the digitization of the RPC signals. While a simple threshold measurement is applied after a fast shaper to count particles, the charge measurement is performed by an analog to digital converter that reads the peak of a slow shaper. An field-programmable gate array is responsible for control of all the digital part which includes storing the MAROC outputs and sending them to a Central Unit [via low voltage differential signal (LVDS)] or PC (via USB). Both the count and charge measurement performance are assessed. The threshold efficiency curve is measured for different temperatures. For all the conditions tested, the efficiency is 100% for charges higher than 52 fC. The overall efficiency to detect muons is studied by placing an RPC between a hodoscope and comparing the efficiency of the front-end with another established data acquisition system. The efficiency results are consistent within the statistical uncertainties of the measurements showing that the MARTA front-end does not introduce unwanted inefficiencies in the setup. The charge measurement is tested in the laboratory using a signal generator. Different shaping conditions and input charges are used to study the waveform of the slow shaper. A linear dependence between input charge and the value measured by the MAROC was found and taken as the calibration curve for the particular channel tested. [ABSTRACT FROM AUTHOR]

The Muon g-2 experiment at Fermilab will measure the muon anomalous magnetic moment $a=(g-2)/2$ to an unprecedented precision of 0.14 parts per million (ppm). To this aim, a calibration system made by a laser source and light distribution will provide short light pulses directly into each crystal of the 24 calorimeters to measure energy and arrival time of the decay positrons. Each calorimeter is composed of a 6\times 9$ matrix of PbF_{2} crystals where each crystal is read by a silicon photomultiplier. Continuous monitoring and state-of-the-art calibration are required in order to control the detector response. The calibration light pulses are monitored, both at the laser output (source monitor) and at the end of the distribution system (local monitor), before delivery to the calorimeters. For example, the light pulses are read by specific photodetectors, whose signals are digitized by electronics designed to match the experimental requirements. All readout electronics boards are hosted in a crate where the controller manages the complete data collection, operates as an event builder and transfers data to the online farm system through a gigabit Ethernet connection. This data acquisition (DAQ) system is designed around a custom protocol and hardware to achieve high data transfer rate and event-building capability without software overhead. In this paper, after a general outline of this DAQ system, we describe in detail the main features of controller. [ABSTRACT FROM AUTHOR]

Neutrinos play a fundamental role in the understanding of the origin of ultrahigh-energy cosmic rays. They interact through charged and neutral currents in the atmosphere generating extensive air showers. However, the very low rate of events potentially generated by neutrinos is a significant challenge for detection techniques and requires both sophisticated algorithms and high-resolution hardware. Air showers initiated by protons and muon neutrinos at various altitudes, angles, and energies were simulated in CORSIKA and the Auger OffLine event reconstruction platforms, giving analog-to-digital convertor (ADC) patterns in Auger water Cherenkov detectors on the ground. The proton interaction cross section is high, so proton “old” showers start their development early in the atmosphere. In contrast to this, neutrinos can generate “young” showers deeply in the atmosphere relatively close to the detectors. Differences between “old” proton and “young” neutrino showers are visible in attenuation factors of ADC waveforms. For the separation of “old” proton and “young” neutrino ADC traces, many three-layer artificial neural networks (ANNs) were tested. They were trained in MATLAB (in a dedicated way -only “old” proton and “young” neutrino showers as patterns) by simulated ADC traces according to the Levenberg–Marquardt algorithm. Unexpectedly, the recognition efficiency is found to be almost independent of the size of the networks. The ANN trigger based on a selected 8-6-1 network was tested in the Cyclone V E FPGA 5CEFA9F31I7, the heart of prototype front-end boards developed for testing new algorithms in the Pierre Auger surface detectors. [ABSTRACT FROM AUTHOR]

The operation of the compact muon solenoid drift tubes (DTs) muon detectors at the high-luminosity large hadron collider will be possible only with an upgrade of the current readout and trigger electronics, which are based on very old technology and directly exposed to radiation, hence particularly sensitive to aging. A new level 1 trigger primitive generator, based on the use of an original compact Hough transform (CHT) algorithm, is being designed with the goal of its implementation in the state-of-the-art field programmabla gate array (FPGA) devices. The algorithm can identify the muon track segment parameters and must be combined with a majority mean-timer in order to assign the muon to its parent bunch crossing. The algorithm is expected to be deployed on FPGAs and has a few \mu \texts latency for decision taking, with efficiency and resolution equal or higher with respect to the ones provided by the currently running algorithm. The major challenges are parallelization of the algorithm, fast readout of the CHT parameter matrix, the capability of handling data from a large array of DTs in the minimal number of FPGAs, and coping with the latency requirements. These issues will be addressed proposing constructive solutions. [ABSTRACT FROM AUTHOR]

A front-end electronics prototype for the ATLAS small-strip Thin Gap Chamber (sTGC) based on gigabit Ethernet has been developed. The prototype is designed to read out signals of pads, wires, and strips of the sTGC detector. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 field-programmable gate array (FPGA) used for the VMM2 configuration and the events storage, and a gigabit Ethernet transceiver PHY chip for interfacing with a computer. The VMM2 chip is designed for the readout of the Micromegas detector and sTGC detector, which is composed of 64 linear front-end channels. Each channel integrates a charge-sensitive amplifier, a shaper, several analog-to-digital converters, and other digital functions. For a bunch-crossing interval of 25 ns, events are continuously read out by the FPGA and forwarded to the computer. The interface between the computer and the prototype has been measured to reach an error-free rate of 900 Mb/s, therefore making a very effective use of the available bandwidth. Additionally, the computer can control several prototypes of this kind simultaneously via the Ethernet interface. At present, the prototype will be used for the sTGC performance test. The features of the prototype are described in detail. [ABSTRACT FROM AUTHOR]

We present first results from a trigger based on the discrete cosine transform (DCT) operating in new front-end boards with a Cyclone V E field-programmable gate array (FPGA) deployed in seven test surface detectors in the Pierre Auger Test Array. The patterns of the ADC traces generated by very inclined showers (arriving at 70° to 90° from the vertical) were obtained from the Auger database and from the CORSIKA simulation package supported by the Auger OffLine event reconstruction platform that gives predicted digitized signal profiles. Simulations for many values of the initial cosmic ray angle of arrival, the shower initialization depth in the atmosphere, the type of particle, and its initial energy gave a boundary on the DCT coefficients used for the online pattern recognition in the FPGA. Preliminary results validated the approach used. We recorded several showers triggered by the DCT for 120 Msamples/s and 160 Msamples/s. [ABSTRACT FROM AUTHOR]

The increase in center-of-mass energy and luminosity for Run-II of the Large Hadron Collider poses new challenges for the trigger systems of the experiments. To keep triggering with a similar performance as in Run-I, the CMS muon trigger is currently being upgraded. The new algorithms will provide higher resolution, especially for the muon transverse momentum and will make use of isolation criteria that combine calorimeter with muon information already in the level-1 trigger. The demands of the new algorithms can only be met by upgrading the level-1 trigger system to new powerful FPGAs with high bandwidth I/O. The processing boards will be based on the new \mu TCA standard. We report on the planned algorithms for the upgraded Global Muon Trigger (\muGMT) which sorts and removes duplicates from boundaries of the muon trigger sub-systems. Furthermore, it determines how isolated the muon candidates are based on calorimetric energy deposits. The \muGMT will be implemented using a processing board that features a large Xilinx Virtex 7 FPGA. Up to 72 optical links at 10 Gb/s will be used to receive muon candidates and energy sums from the calorimeter trigger. Muon candidates will be received directly from the sector processors of the upgraded trigger, absorbing the final sorting stage of each muon sub-system and thus minimizing the latency of the trigger. [ABSTRACT FROM PUBLISHER]

High-energy physics experiments at the high-intensity frontier place ever-greater demands on detectors, and in particular on tracking devices. In order to compare the performance of many possible small-size tracking prototypes, a high-resolution cosmic ray tracker may be used as an external track reference. We have constructed a telescope by assembling four spare ladders of the external layers of the Silicon Vertex Tracker of the BaBar experiment. This test facility, operating at INFN Sezione di Pisa, provides the detector under test with an external track with an intrinsic resolution of 15–30 ~\mu\m. The DAQ originally used in the BaBar experiment was replaced by custom-designed boards coupled with an acquisition front-end personal computer through commercial field-programmable gate array evaluation boards. We show that the facility is operative, and we present the performance in terms of tracking resolution and efficiency. A first device has been characterized, and some plots from the analysis demonstrating the telescope performance are shown. [ABSTRACT FROM PUBLISHER]

The paper describes the prototype of a synchronous (Master/Slave) data acquisition system for underground muon counters triggered by surface detectors. A water Cherenkov surface detector (Master) when hit by extensive air showers generates and transmits the trigger to the underground system (Slave) to register the muon fraction of the showers which survived the propagation through 3 m layer of soil. The surface and underground segments are built on the Altera field-programmable gate array (FPGA) CycloneIII/CycloneIV platforms, respectively. Both FPGAs are equipped with NIOS processors, which makes previously used external microcontrollers unnecessary. They also generate necessary interfaces: SDRAM controller, UART, SPI, DMA; interfaces which were previously implemented by means of logic elements. Moving several time-consuming tasks from the logic block (coded in the Altera Hardware Description Language) to the NIOS (coded in “C”) dramatically simplifies the system and increases its flexibility. The time margin for all processes managed by the soft-core NIOS for the 100 Hz T1 trigger rate remains sufficient. NIOS processors communicate with each other via UART protocol and by the RS485 standard. The underground CycloneIV FPGA is programmed remotely via additional MAXII CPLD with nonvolatile programmable memory. Tests have shown that a full string of data processing goes smoothly. The above-mentioned string involves the following processes: the transfer of the trigger with a time stamp from the surface detector into the underground segment via a dedicated line with a galvanic barrier, freezing data from 64 channels at 320 MHz sampling in internal DPRAMs, writing/reading data into/from external SDRAM, extracting physical data identified by GPS time stamps sent from Central Data Acquisition System (CDAS) and the data transfer from the underground NIOS via the surface NIOS to CDAS. [ABSTRACT FROM PUBLISHER]

The trigger based on the Discrete Cosine Transform (DCT) allows recognition of ADC traces of a specific shape i.e., with a very short rise time and fast exponential attenuation related to a narrow, flat muon component of very inclined extensive air showers generated by hadrons and starting their development early in the atmosphere (“old” showers). Showers, crossing a surface detector composed of water Cherenkov tanks, such as those in the Pierre Auger Observatory generate Cherenkov light, which may hit photomultipliers (PMTs) directly or after several reflections. The geometry of the water Cherenkov tank imposes a type of the filter preferring the detection of very inclined showers (with very large zenith angle), where mainly two PMTs can be hit by direct light. The 3rd PMT is then hit by reflected light, but with some delay. For the fast sampling (80 MHz), this delay causes the signal to appear in the next time bin. Two-fold coincidences of DCT coefficients allow triggering signals that are ignored at that time due to either too high an amplitude threshold for three-fold coincidences in a single time bin (the standard Auger threshold trigger) or due to the de-synchronization of the signals in time caused by the tank geometry (delay on one or more time bins due to a longer light path corresponding to the reflection on the tank walls). Three DCT engines implemented into EP3C40F324I7 FPGA use all DSP blocks and generate the spectral trigger, when 8 DCT coefficients simultaneously are inside the acceptance lane in at least 2 channels. An additional veto signal (analyzing the amplitude) controls the trigger rate to avoid a saturation of a transmission channel. In a test performed in the Pierre Auger laboratory in Malargue (Argentina), the spectral trigger has been tuned for shapes corresponding to “old” showers. Both laboratory and long-term field measurements on a test tank confirmed a high efficiency of the recognition of expected patterns of ADC traces. The patterns of the spectral trigger for “young” showers are being optimized in simulations. We expect to detect “young” showers close to their cores. [ABSTRACT FROM AUTHOR]

The upcoming Belle II experiment is designed to work at a luminosity of 8\times 10^35 cm^-2s^-1, 40 times higher than its predecessor. The pixel detector of Belle II with its \sim8 million channels will deliver ten times more data than all other sub-detectors together. A data rate of 22 Gbytes/s is expected for a trigger rate of 30 kHz and an estimated pixel detector occupancy of 3%, which is by far exceeding the specifications of the Belle II event builder system. Therefore a realtime data reduction of a factor > 30 is needed. [ABSTRACT FROM AUTHOR]

The aim of the AMIGA project (Auger Muons and Infill for the Ground Array) is an investigation of Extensive Air Showers at energies lower than those accesible with the standard Auger array, where the transition from galactic to extragalactic sources is expected. The paper describes the working principle of the Master/Slave (standard Auger surface detector/the underground muon counters) synchronous data acquisition and general triggering applied in two prototypes: with 12.5 ns resolution built from 4 segments (2 FPGAs and 2 standard micro-controllers) and 3.125 ns resolution built from two segments only (2 FPGAs with implemented NIOS® processors). [ABSTRACT FROM PUBLISHER]

The Daya Bay RPC (Resistive Plate Chamber) readout system is responsible for collecting event data created by muons entering the detector systems from above. The readout system should be capable of converting analog signals from the RPC detectors into digital signals, which are buffered and uploaded for readout by the online DAQ (Data Acquisition) system. The RPC readout system will report trigger information to a master trigger system. The numerous and relatively minute pulses from the RPC detectors require accurate signal discriminating and reliable data transmission. This article provides a brief overview of the Daya Bay RPC detector and then outlines the design and performance of the prototype RPC readout system. [ABSTRACT FROM AUTHOR]