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International audience; This paper investigates laser and heavy ion irradiation effects on Perpendicular Magnetic Anisotropy Spin Transfer Torque Magnetic Tunnel Junction devices (PMA STT-MTJ). The Radiative campaign will take place at the Université Catholique de Louvain (UCL) facility in April 2020. The considered devices consist of STT p-MTJs purely magnetic memories and they were fabricated using the most advanced CoFeB-MgO MTJ technology. Single-event upset (SEU) tolerance and modification of magnetic properties will be deeply investigated and presented in the final paper.

International audience; This paper presents a dual-modular-redundancy and dual-level error-interception based triple-node-upset (TNU) tolerant latch design (namely DDETT) for safety-critical applications. The DDETT latch comprises two parallel single-node-upset self-recoverable cells to store values and three C-elements to intercept errors. Both of the two cells are constructed from triple mutually-feeding-back 2-input C-elements, and the cells feed two internal C-elements for first-level error-interception. Moreover, the two internal C-elements feed an output-stage C-element for second-level error-interception, making the DDETT latch TNU-tolerant in that it can tolerate any possible TNU. This paper further presents a low-cost version of the DDETT latch, namely LCDDETT. The LCDDETT latch uses two dual-interlocked-storage-cells (DICEs) to store values and uses dual-level error-interception to tolerate any possible TNU with cost-effectiveness. Simulation results not only confirm the TNU-tolerance of the proposed latches but also demonstrate that the delay-power-area products of the DDETT and LCDDETT latches are reduced by approximately 34% and 58%, respectively.

International audience; Germanium is potentially candidate to replace silicon in ultra-scaled transistors. This work analyses the radiation response of germanium in thin layer subjected to atmospheric neutrons simulated with Geant4 and quantifies the underlying mechanisms potentially responsible of single event effects in Ge-based CMOS technologies. From this analysis of interactions at material-level, reliability assessments for Gebased nanoelectronics are tentatively deduced for technological nodes ranging from 180 nm to 5 nm in terms of nature and number of nuclear events susceptible to upset a SRAM memory cell. Finally, first soft error rate projections are performed for germanium SRAMs in 130, 65 and 40 nm based on a simulation methodology previously developed and fully validated on silicon memories also characterized by real-time experiments.

International audience; Machine learning (ML) algorithms have been regaining momentum thanks to their ability to analyze substantial and complex data, supporting artificial intelligence decisions in cloud computing but also in near-sensor computing in endpoint devices. Both cloud and near-sensor computing are liable to radiationinduced soft errors, especially in automotive and aerospace safety-critical applications. In this regard, this paper contributes by comparing the accuracy of tw o prominent machine learning algorithms running on a lowpow er processor upset by radiation-induced soft errors. Both ML algorithms have been assessed w ith the help of a fault injectionbased method able to natively emulate soft errors directly in a development board. In addition, neutron radiation test results suggest the most critical situations in w hich mitigation solutions should address.

International audience; To meet the requirements of both high reliability and low power in low-orbit aerospace applications, this article first presents a single-event Double-Upset (SEDU) self-Recoverable and single-event Transient (SET) Pulse Filterable (DURTPF) latch design with low power. The DURTPF latch mainly consists of eight mutually feeding-back C-elements (CEs) and an SET pulse filterable Schmitt-trigger (ST). To make an ST behave not only as a pulse filterable ST but also as an error interceptive CE, an input-split ST is created, leading to an enhanced-version of the DURTPF latch, namely DURTPF-EV. The DURTPF-EV latch mainly consists of seven mutually feeding-back CEs including an input-split ST. Simulation results demonstrate both the SEDU self-recoverability and SET pulse filterability of the proposed latches at the cost of moderate silicon area. Using the clock gating technology, the DURTPF latch reduces power dissipation by about 63% on average compared with the state-of-the-art SEDU self-recoverable latch designs that are not SET-pulse filterable. Moreover, the DURTPF-EV latch is more cost-effective and its reliability is also enhanced, making it more suitable for low power and low-orbit aerospace applications.

International audience; With the rapid advancement of CMOS technologies, nano-scale CMOS latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations. First, this paper proposes a novel latch design, namely QNUTL that can completely tolerate MNUs such as double-node upsets, triple-node upsets (TNUs), and even quadruple-node upsets (QNUs). The latch is mainly constructed from three dual-interlocked-storage-cells (DICEs) and a triple-level soft-error interceptive module (SIM) that consists of six 2-input C-elements. Due to the single-node-upset self-recoverability of DICEs and the soft-error interception of the SIM, the latch can completely tolerate any QNU. Next, by replacing the DICEs in the QNUTL latch by clock-gating (CG) based ones, a QNUTL-CG latch is proposed to significantly reduce power consumption. Simulation results demonstrate the MNU-tolerance of the proposed latches. Moreover, owing to the use of a high-speed transmission path, clock-gating, and a few transistors, the proposed QNUTL-CG latch has low overhead in terms of area, D-Q delay, CLK-Q delay, and setup time, compared with the state-of-the-art TNU-tolerant latch (TNUTL) which is not QNU-tolerant.

This article proposes to study the impact of ground-level enhancement (GLE) induced by extreme solar flares on the soft error rate (SER) for flight representatives to the world-air traffic. A GLE physical model was confronted to cosmic ray variations measured with neutron monitors during the GLEs 5 and 69. Based on said GLE physical model and single-event upset occurrence models, investigations were performed to assess the SER during these GLEs for a bulk 90-nm commercial off-the-shelf SRAM. The main conclusion is that the GLE impact must be considered in the risk assessment, which requires a physical description of the additional solar cosmic rays and a realistic consideration of the air traffic.

International audience; The paper investigates radiation-induced switching mechanisms, temperature effects, breakdown voltage, sensitive volume and critical charge definitions for Spin-Transfer Torque Magnetic Tunnel Junction. Thermal spike model is adopted to estimate the temperature reached during heavy ion irradiation and temperature effects are suggested to be responsible for the magnetic properties degradation and for upset processes.

International audience; This paper describes the deployment and optimization process of triple-module redundancy(TMR) under high design constraints against single-event upset (SEU) and single-eventtransient (SET). It includes modelling of single-event effect (SEE) pulses with TCAD meshmodel, TMR deployment strategies, and verification methods. The simulation result showsthat the prototype system with optimized TMR deployment has high reliability with respectto design requirements. The system can run for more than 5 years without critical errorswith an equivalent error rate in the working environment is lower than 10$^{-9}$ .

International audience; This paper presents two novel quadruple cross-coupled memory cell designs, namely QCCM10T and QCCM12T, with protection against single event upsets (SEUs) and double-node upsets (DNUs). First, the QCCM10T cell consisting of four cross-coupled input-split inverters is proposed. The cell achieves full SEU tolerance and partial DNU tolerance through a novel feedback mechanism among its internal nodes. It also has a low cost in terms of area and power dissipation mainly due to the use of only a few transistors. Next, based on the QCCM10T cell, the QCCM12T cell is proposed that uses two extra access transistors. The QCCM12T cell has a reduced read-and-write access time with the same soft error tolerance when compared to the QCCM10T cell. Simulation results demonstrate the robustness of the proposed memory cells. Moreover, compared with the state-of-the-art hardened memory cells, the proposed QCCM12T cell saves 28.59% write access time, 55.83% read access time, and 4.46% power dissipation at the cost of 4.04% silicon area on average. INDEX TERMS Double-node upset, memory cell, radiation hardening, single event upset, soft error.

International audience; The sensitivity of memory devices under proton irradiation has been extensively studied over the years. Two main mechanisms have been identified to drive the single-event upset (SEU) sensitivity in the last generation of devices: direct ionization for low proton energies and inelastic nuclear reactions for higher proton energies. Some papers have shown that the Coulomb elastic contribution should be considered. This paper supports this conclusion and proposes analyses in order to show the importance of this contribution according to the technological node studied.

International audience; This paper highlights the impact of design on the single-event upset (SEU) sensitivity of D-flip-flops (DFFs) used in a readout circuit (ROIC) under heavy ions. New experimental data obtained at the University of Louvain for several designs are presented. The single-event effect (SEE) prediction tool multi-scale single event phenomena predictive platform is used to investigate the failure occurrences at the circuit level as a function of the design. In some cases, design specificities allow for increasing in the SEU robustness of the DFF. However, it appeared that cryogenic temperatures limit the impact of the design on the SEU sensitivity of DFFs.The results show a very limited impact of the temperature on the SEU occurrence, independent of the layout. These results are consistent with the experimental data presented in recent works regarding single-event transient and single-event functional interrupt. These results allow for performing irradiation tests of complementary metal-oxide-semiconductor IR detector (ROIC) at room temperature instead of cooling down the device during the SEE measurements.

International audience; In this paper the impact of the muon radial ionization profile on Single-Event Upset (SEU) sensitivity for nanoscale technologies is investigated with simulations and experimental measurements. The physical model used in the simulation framework is compared with experimental measurements of the charge deposit induced by atmospheric particles on a CCD pixel array. This scientific instrument is used to monitor the atmospheric muons, and allows to investigate the charge deposition induced by muon of micrometric sensitive volumes (i.e. the CCD pixel). Atmospheric and underground sites are considered for monitoring pixel-charge events and the combined analysis of the data is used to discriminate muons from other particles. 3D descriptions of muon tracks were simulated with radiation transport code Geant4, and coupled with Single Event Effect (SEE) simulation based on multi-physics approaches (MUSCA SEP3) to investigate the SEU cross-section and Soft Error Rate (SER) trends as function of technological downscaling. SER trends are analyzed for bulk technologies, from 65 to 14 nm integration nodes, in both ground and avionic environments. Results show that for technologies whose characteristic lengths are greater than 50 nm, it is not necessary to consider radial energy deposit structure of muon in SEE assessment. At ground, downscaling of the technological node induces an increase in the SEU susceptibility to cosmic ray showers, mainly because of muons. For nanoscale devices operating at avionic altitude, the muon contribution to the SER is very weak in comparison of the proton and neutron contributions.

28th European Symposium on the Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Bordeaux, FRANCE, SEP 25-28, 2017; International audience; Altitude and underground real-time soft error rate (SER) measurements on SRAM circuits have been analyzed in terms of independent multi-Poisson processes describing the occurrence of single events as a function of bit flip multiplicity. Applied for both neutron-induced and alpha particle-induced SERB, this detailed analysis highlights the respective contributions of atmospheric radiation and alpha contamination to multiple cell upset mechanisms. It also offers a simple way to predict by simulation the radiation response of a given technology for any terrestrial position, as illustrated here for bulk 65 nm and 40 nm SRAMs. (C) 2017 Elsevier Ltd. All rights reserved.

53rd IEEE Nuclear and Space Radiation Effects Conference (NSREC), Portland, OR, JUL 11-15, 2016; International audience; We address accurate computation of on-orbit upset rates in advanced technologies, with a focus on FD-SOI at the 28 nm node. Heavy-ion measurements performed on FD-SOI SRAM bit-cells give experimental evidence of the technology's intrinsic robustness in space environments; this extreme reduction of sensitive volume dimensions deeply affects the assumptions pertaining to the radiation response models used to predict upset rates. The generic ``Integral Rectangular Parallele Piped''(IRPP) model, although requiring careful setting of its parameters, provides us with first-order estimates of the error rate. We then present a custom FD-SOI response model within our Monte-Carlo simulation chain, enabling comparison with IRPP and further analyses.

International audience; Inserting hardware Trojans (HT) in ring oscillators (RO) of integrated systems is a malicious method that can considerably modify the behaviour of system circuits to produce undesired operations. This work presents and demonstrates three still unknown types of transistor-level Trojans based on the classic tri-state logic. If triggered, the presented HT are able to substantially change the jitter and frequency of RO. If disabled, thanks to their tri-state logic and tiny sizes, the circuit behaviour is not significant modified, making the Trojan detection through conventional functional testing or side-channel analysis unlikely. Results show the typical frequency of a 7-stage RO in CMOS 65-nm technology is kept within process corners if HT is off, and it is decreased by a factor of up to 0.7 when HT is on.

International audience; A 2-D axisymmetric finite element model of upset resistance welding on tube to rod configuration is developed. It is based on an electrical-thermal-mechanical analysis and developed on commercial software MARC for nuclear fuel pin cladding welding application. It allows to assess local temperature and strain fields during welding. A parameter influence study reveals, among others, the importance of contact resistances between samples and electrodes. Some contact resistance models are proposed and a specific calibration method of those models, which implies experimental tests and numerical simulations, is developed. This calibration method allows to obtain a good agreement between the welding simulation and the relevant instrumented experiment for two different studied geometries.

A methodology is proposed for the statistical analysis of memory radiation test data, with the aim of identifying trends in the single-even upset (SEU) distribution. The treated case study is a 65nm SRAM irradiated with neutrons, protons and heavy-ions.

International audience; Various failure scenarios may occur during irradiation testing of SRAMs, which may generate different characteristic Multiple Cell Upset (MCU) error patterns. This work proposes a method based on spatial and temporal criteria to identify them.

International audience; This paper investigates the impact of terrestrial radiation on soft error (SE) sensitivity a long the very large-scale integration (VLSI) roadmap of bulk,FDSOI and finFET nano-scale technologies using the MUSCA SEP3 tool. The terrestrial radiation considered in this work includes neutron, proton, and muon particles and alpha-emitters.The results indicate that protons and muons must be taken into account for ground environments.However, significant differences were observed for bulk, FDSOI and FinFET technologies. The down-scaling induces an increase in SEU susceptibility to radiation. An overall analysis indicates that the SER does not increase drastically with technological integration for the three technologies considered.More over, the results show that FDSOI and FinFET technologies provide resistance to the ionizing radiation effects due to narrow sensitivity volumes. At the ground altitudes, the total SER ranges from 10e3 and 10e4 FIT/Mbit for the planar bulk technology while it ranges from 10² and 10e3 FIT/Mbit for the FDSOI and FinFET technologies.The results of analyses show that for the avionic altitude, neutron and/or the proton environments induce the main contribution to the total SER, where as muon and α-SER impacts are negligible. For the 45-nm technological node (all types), the neutron contribution is around 60–70% of the total SER.Concerning the ground altitude, α-SER is the main contribution down to the 28-nm node. Moreover, the results suggest muon-induced upset affects the soft error rate from 32-nm SRAM operated at a nominal supply voltage and has a significant impact for circuits fabricated in smaller process technologies (22-nm and 14-nm). In addition, the results show that the muon impact can be the main contribution at 22-nm and beyond. Future terrestrial error rate predictions will require characterizations of the linear energy transfer (LET) threshold with consideration of muon and/or proton environments.

International audience; This paper presents experimental characterization of the impact of negative bias temperature instability on the single-event upset sensitivity of SRAM cells embedded in a 65 nm CMOS test vehicle. Pre and post-aging SEU threshold laser energy measurements indicate that the cells sensitivity increases over time. The results are confirmed by electrical simulation and the consequences in terms of SEU rate prediction are discussed.

Evaluating the sensibility of a given circuit with respect to soft errors became a main issue especially if it is intended to operate in space or at high altitudes. A hardware/software (HW/SW) approach to study the effects of soft errors by fault injection in the VHDL model of a CPU (Control Processor Unit) is presented and illustrated by results obtained for a LEON3 processor. The LEON3 is set to execute two benchmark algorithms. The first one is a typical 3x3 matrix multiplication, whereas the second one is a self-converging algorithm which is intended to provide correct results even if a failure occurs in the middle of the execution. The results of fault-injection campaigns targeting the register file unit of the processor are compared to those issued from a state-of-the-art method, the C.E.U. (Code Emulated Upset). One of the main advantages of the proposed method is the larger targeted Single Event Upset (SEU) sensitive area leading to improved error rate predictions.

This work provides reliability criteria to detect and diagnose multi-events upset by the use of a SER tool. The study is based on a charge generation model used to simulate the impact of an ionizing particle striking the sensitive nodes of a SRAM cell. The currents, collected at the sensitive nodes are generated by the physical model and injected at circuit level. Thus, a correlation between the circuit electrical behavior and injected currents is established to provide a reliability criterion.

International audience; The single-event upset (SEU) fault tolerance of a benchmark self-converging algorithm is evaluated by fault injection campaigns performed using a devoted test platform. The number of observed errors significantly decreases depending on adopted implementation strategies.

ISBN : 978-2-84813-137-5; The reduction of electrical parameters of transistors, resulting of the progress done in the IC's manufacturing technologies, make present and future devices more and more sensitive to transient perturbations, so-called S.E.E. (Single Event Effects) provoked as the consequence of the current pulse issued from the impact with sensitive areas of the circuit, of energetic particles present in the environment where the circuit operates [1]. Among the different types of S.E.E. can be mentioned the SEU (Single Event Upsets) which consist in the inversion of the content of memory cells, the SEL (Single Event Latchup) which may lead to the device destruction as the consequence of thermal effects. This thesis aims at giving a description and validating the methodologies required to estimate the sensitivity to radiations of two types of digital integrated circuits, processors and memories, components used in embedded systems.; La réduction des dimensions et paramètres électriques des transistors, fruit des progrès dans les technologies de fabrication de circuits intégrés, rend les composants présents et futurs de plus en plus sensibles aux perturbations appelées évènements singuliers S.E.E. (Single Event Effects). Ces événements sont la conséquence d'une impulsion de courant résultant de l'impact dans des zones sensibles du circuit, de particules énergétiques présentes dans l'environnement dans lequel ils fonctionnent. Parmi les différents types de SEE, peuvent être mentionnés les SEU (Single Event Upsets) qui consistent en l'inversion du contenu de cellules mémoires, les SEL (Single Event Latchups) qui donnent lieu à des courts-circuits masse-alimentation et peuvent donc conduire à la destruction du circuit par effet thermique. Cette thèse a pour but de décrire et valider les méthodologies nécessaires pour évaluer de manière précise la sensibilité face aux radiations de deux types de circuits numériques représentatifs, processeurs et mémoires, composants utilisés dans la plupart des systèmes embarqués.

The reduction of electrical parameters of transistors, resulting of the progress done in the IC's manufacturing technologies, make present and future devices more and more sensitive to transient perturbations, so-called S.E.E. (Single Event Effects) provoked as the consequence of the current pulse issued from the impact with sensitive areas of the circuit, of energetic particles present in the environment where the circuit operates [1]. Among the different types of S.E.E. can be mentioned the SEU (Single Event Upsets) which consist in the inversion of the content of memory cells, the SEL (Single Event Latchup) which may lead to the device destruction as the consequence of thermal effects. This thesis aims at giving a description and validating the methodologies required to estimate the sensitivity to radiations of two types of digital integrated circuits, processors and memories, components used in embedded systems., La réduction des dimensions et paramètres électriques des transistors, fruit des progrès dans les technologies de fabrication de circuits intégrés, rend les composants présents et futurs de plus en plus sensibles aux perturbations appelées évènements singuliers S.E.E. (Single Event Effects). Ces événements sont la conséquence d'une impulsion de courant résultant de l'impact dans des zones sensibles du circuit, de particules énergétiques présentes dans l'environnement dans lequel ils fonctionnent. Parmi les différents types de SEE, peuvent être mentionnés les SEU (Single Event Upsets) qui consistent en l'inversion du contenu de cellules mémoires, les SEL (Single Event Latchups) qui donnent lieu à des courts-circuits masse-alimentation et peuvent donc conduire à la destruction du circuit par effet thermique. Cette thèse a pour but de décrire et valider les méthodologies nécessaires pour évaluer de manière précise la sensibilité face aux radiations de deux types de circuits numériques représentatifs, processeurs et mémoires, composants utilisés dans la plupart des systèmes embarqués.

International audience; This paper describes two different but complementary approaches that can be used to perform SEU-like fault injection sessions in order to predict error rates of digital processors. The Code Emulated Upset (CEU) approach allows fault injection in processor memories (caches and register files), while the FPGA Autonomous Emulation approach allows fault injection in processor flip-flops. Results obtained for a case studied, the LEON processor, illustrate the complementary aspects of proposed strategies.

In this paper are first summarized representative examples of anomalies observed in systems operating on-board satellites as the consequence of the effects of radiation on integrated circuit, showing that single event upsets (SEU) are a major concern. An approach to predict the sensitivity to SEUs of a software application running on a processor-based architecture is then proposed. It is based on fault injection experiments allowing estimating the average rate of program dysfunctions per upset. This error rate, if combined with static cross-section figures obtained from radiation ground testing, provides an estimation of the target program error rate. The efficiency of this two-step approach was demonstrated by results obtained when applying it to various processors.

The off-NMOS and off-PMOS transistor single-event upset (SEU) sensitivities are studied in a 0.6-/spl mu/m SRAM. In some cases, the off-PMOS sensitivity is shown to be similar to the off-NMOS one. This could affect SEU rate calculations.

International audience; A Monte Carlo approach is used to obtain statistical information on the effect of the spatial distribution of the numerous secondary ions involved in neutron induced soft error rates (SER). The sorting criteria for the occurrence of upset are derived from a simplification of previous work on full-cell three-dimensional (3-D) SRAM device simulation. The time thus saved allows the treatment of a wide variety of track conditions. The shape and extension of the sensitive region is explored and correlated to the secondary ion properties. Details on the variations of the sensitivity with depth into the sensitive region as well as on the geometrical conditions associated with those tracks that cause upsets are given.

Results from fault injection experiments on a modern complex processor, the PPC7400, are combined with static register ground testing to predict single-event upset rates of several benchmark application programs. These results compare favorably with in-beam measurements on the same programs.

International audience; When exposed to an harsh environment in space, high atmosphere or even on earth, Integrated Circuits undergo soft errors. Among these events the most worrying is an electrical upset, so called Single Event Upset (SEU) evidenced in latches. We present here the circuit architecture of a new SEU hardened latch. The hardening is based on an integrated redundancy of the information and a high impedance state switching. The design prevents perturbation to propagate inside the latch and saves an uncorrupted information source for recovery mechanisms. Post layout circuit simulations are used to verify the hardness assurance of this design; we also compare it to usual techniques and report significant improvements for its use in SoC.

Various single-event upset (SEU) conditions are studied by three-dimensional device simulation with the purpose of going deeply into the understanding of the mechanisms governing the SEU sensitivity for a large variety of tracks. The results give a better view of what regions are sensitive. They clearly point out that some generally accepted notions must be revised as considering the normal incidence case to be the most sensitive or neglecting PMOS contribution.

International audience; The purpose of this work is to present one investigation utilizing a pulsed laser as a tool to improve the Single Event Upset tolerance of a memory cell. These results coming with a previous ion testing evaluation of the circuit allow an optimization of the design. The laser results permit a more detailed analysis of the phenomenon leading to the upset and a precise localization of the most sensitive areas. As a result the behavior verification of the design combined with the use of robust elementary blocks strengthens the hardening capabilities of the cell.

Single-event upsets (SEUs) in static random access memories (SRAMs) are investigated using three-dimensional (3-D) full cell device simulations for tracks that do not cross the OFF n-channel MOSFET drain. These tracks are representative of the most probable geometrical cases when the ions are generated inside the device by nuclear reactions, and then address one important part of neutron- or protons-induced soft errors. It is found that the duration and magnitude of the ion-induced current pulse strongly depends on the track location. As a result, the flipping of the memory cell is delayed, and the critical charge involved during the upset is no longer constant. A linear relationship between the critical charge and the delay is found and is explained by the contribution of the ON p-channel MOSFET. The increase of the ion current pulse delay and broadening when the track is moved away from the drain is explained on the basis of the diffusion-collection mechanism. Indications on the size of the sensitive regions are derived.

A test vehicle has been specially realized to demonstrate that different physical mechanisms are responsible for single-event upset phenomena within an elementary memory cell, depending on the impact location. Validation is performed using pulsed laser equipment.

Investigates an approach allowing one to evaluate the consequences of single event upset phenomena for the reliable operation of processors. The method is based on the simulation of bit flips using a modified version of a high-level circuit description. Preliminary results illustrate the potential of this new strategy.

The SEU hardness of a new CMOS storage cell based on latch redundancy has been analyzed using a laser beam simulation. We detected and investigated topology-dependent upset mechanisms due to charge collection at two sensitive nodes using a laser excitation between the nodes. Compact upset-immune device topologies are proposed, using spacing and isolation techniques for simultaneously sensitive node pairs, to achieve high immunity levels required in critical applications.

With the increasing complexity of treatments on satellite-borne and the utilisation of highly integrated circuits, the upset phenomenon becomes more and more crucial. Indeed, this phenomenon, caused by a heavy ion strike results in the modification of the information stored in a memory element. Upsets may perturb the operation of satellite-borne applications and can lead to serious consequences on the control of equipment operating in space. Artificial neural networks (ANN) constitute a new approach in information processing. They offer powerful and compact solutions to a wide range of problems, in particular those with real time constraints which is the case for most of current space applications. Among the main properties of neural networks we can mention their fault tolerance which measures their capability to perform the desired task under fault conditions (erroneous information) and to maintain their computing ability when a part of the network is damaged or removed. The goal of this thesis is to study the fault tolerance of neural networks against single event upsets in order to investigate the possibility of their utilisation in a radiative environment such as space. This work aims mainly at choosing, among the tested circuits, those that are accepted (or rejected) for space applications. Several networks and several circuits have been tested. Three kinds of experiments have been performed: software simulation of errors, hardware injection of faults and heavy ions tests. Obtained results show that Artificial Neural Networks are tolerant against upsets which make them a good candidate for use in space applications., Avec l'accroissement de la complexité des traitements effectués à bord des véhicules spatiaux et l'utilisation de circuits de plus en plus intégrés, le phénomène d'upset devient de plus en plus critique. En effet, ce phénomène se traduit par le basculement intempestif du contenu d'un point mémoire suite à l'impact d'une particule lourde dans des zones sensibles du circuit. Ses conséquences sont parfois fatales et peuvent conduire à la perte voire à la destruction de l'engin sur lequel il a eu lieu. Les réseaux de neurones artificiels constituent une nouvelle approche de traitement de l'information. Ils offrent des solutions compactes et rapides pour une large gamme de problèmes, en particulier ceux ayant des contraintes temps réel tel le cas de la plupart des applications spatiales actuelles. Ceci est davantage vrai avec l'utilisation des émulations et des implantations matérielle. Parmi les propriétés importantes des réseaux de neurones, on peut citer leur tolérance aux fautes qui mesure leur aptitude à exécuter la tâche qui leur est demandée en présence d'informations erronées et de maintenir leur capacité de calcul même si une partie du réseau est endommagée. L'objectif de cette thèse est d'étudier la tolérance aux fautes des réseaux de neurones face aux fautes de type upset et ceci en vue d'étudier la possibilité de leur utilisation, sous forme matérielle, dans un environnement radiatif tel que l'espace, le but étant de choisir parmi des circuits candidats, ceux qui sont acceptés (ou rejetés) pour des applications spatiales. Pour ce faire, plusieurs réseaux et plusieurs circuits ont été testés. Les expériences réalisées étaient de type simulation logicielle d'erreurs, injection matérielle de fautes et tests aux ions lourds. Les résultats obtenus montrent que les réseaux de neurones artificiels sont tolérants aux fautes de type upsets ce qui en fait un bon candidat pour les applications s'exécutant à bord des engins spatiaux.

Artificial Neural Networks have been shown to possess fault tolerant properties. We present the architecture of a neural network designed to process satellite images (SPOT photos). Computer simulations and ground tests performed on a digital implementation of this neural network prove its robustness with respect to bit errors.

A novel design technique is proposed for storage elements which are insensitive to radiation-induced single-event upsets. This technique is suitable for implementation in high density ASICs and static RAMs using submicron CMOS technology.

Laser tests performed on a prototype chip to validate new SEU-hardened storage cell designs revealed unexpected latch-up and single-event upset phenomena. The investigations that identified their location show the existence of a topology-dependent dual node upset mechanism. Design solutions are suggested to avoid its occurrence.

NUMBER OF PAGES: xii+1011; This paper presents implementation and test experiments of a current monitoring technique for on-line detection and correction of transient faults in CMOS static RAMs. This technique combines built-in current sensing (BICS) with parity code to achieve zero detection latency and single-bit error correction.

ISBN: 0818655208; We present a new technique to improve the reliability of SRAMs used in space radiation environments. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of the memory cell being upset. The current checking is performed on the SRAM columns and it is combined with a single-parity bit per RAM word to perform error correction.

The main part of this paper describes upside metallurgical and mechanical work done at SNECMA, on inertia welding of powder metallurgy nickel base superalloys ASTROLOY and N18, allowing appliance of this process to engine parts: Inertia welding of superalloys leads to deep microstructural changes in the H.A.Z. which have been, as well as upset, correlated to process parameters, weld geometry and base material microstructure; a full mechanical testing of welds shown properties equivalent to base material ones up to 650 o C except for fatigue crack growth behavior under specific conditions (T>600 o C-hold time at maximum load) which is drastically reduced for in weld plane propagation. A significant improvement of thislater property has been done through post-welding heat treatment and optimization of welding parameters. Last part of this paper summarize the main teachings gained, on the complete welding procedure, from welding of scale one parts

Microprocessor sensitivity to the upset phenomenon has been generally evaluated by enumerating the bit modifications of programmer accessible registers, due to circuit irradiation with heavy-ions. For current 32-bit processors these registers represent only a little part of the sensible area. The authors' work aims at comparing the upset cross-section obtained when the tested microprocessor is exercised with commonly used register tests, to those obtained using test programs that activate more thoroughly the circuit memory elements. Experimental results of upset tests performed on two different microprocessors. The MC 68020 and the SPARC MHS 90C601, and the corresponding floating-point coprocessors (the 68882 and the 90C602) are presented. >

2014 The compressibility of solids, subjected to hydrostatic pressures, is determined by the measurement of the inductance of a coil in intimate contact with the surface of the sample. However, it is necessary to observe certain experimental conditions, which are closely examined. Good adherence between the coil and its support is of major importance, especially in a liquid pressure transmitting medium. Measurements are also upset by electromagnetic interactions between the coil and the pressure vessel. It was found theoretically and verified experimentally that these interactions can be cancelled. Two experimental factors : the use of a liquid transmitting medium and the measurement in situ of the presure, are of major importance for the reproductibility and the sensibility of the method. Application to the Pyrex glass. REVUE DE PHYSIQUE APPLIQUEE TOME 10, JANVIER 1975, PAGE Classification Physics Abstracts 0.632

L'environnement radiatif spatial provoque des anomalies dans les systèmes informatiques embarques. Il est donc primordial de définir des stratégies de qualification permettant le choix du circuit le moins vulnérable. Le phénomène dit d'Upset est l'un des effets du rayonnement le plus critique pour les circuits intégrés. Les différentes stratégies de test d'Upset sont passées en revue, dans le cas des circuits intégrés programmables. Un équipement expérimental de test a été développé et une methode de test a été appliquée a des circuits candidats a des applications spatiales. Les tests aux ions lourds ont été réalisés a l'aide de différents simulateurs d'ions lourds (source de californium, cyclotron, synchrotron), validant ainsi le matériel et l'approche développes et donnant des indications sur l'efficacité de ces simulations