Search

Your search keyword '"Maintenance testing"' showing total 9 results
Start Over Descriptor "Maintenance testing" Publisher hal ccsd
9 results on '"Maintenance testing"'

1. Maintenance Cost Models

Author

Alaa Chateauneuf, Franck Schoefs, Institut de Recherche en Génie Civil et Mécanique (GeM), Université de Nantes - UFR des Sciences et des Techniques (UN UFR ST), Université de Nantes (UN)-Université de Nantes (UN)-École Centrale de Nantes (ECN)-Centre National de la Recherche Scientifique (CNRS), Judith Baroth, Franck Schoefs, Denys Breysse, Laboratoire de Mécanique et Ingénieries (LAMI), Institut Français de Mécanique Avancée (IFMA)-Université Blaise Pascal - Clermont-Ferrand 2 (UBP), Contrôle de santé fiabilité et calcul des structures (TRUST), Université de Nantes - Faculté des Sciences et des Techniques, and Université de Nantes (UN)-Université de Nantes (UN)-École Centrale de Nantes (ECN)-Centre National de la Recherche Scientifique (CNRS)-Université de Nantes - Faculté des Sciences et des Techniques

Subjects
021110 strategic, defence & security studies, Engineering, business.industry, Process (engineering), 0211 other engineering and technologies, Deferred maintenance, Operational maintenance, 020101 civil engineering, 02 engineering and technology, [SPI.MECA]Engineering Sciences [physics]/Mechanics [physics.med-ph], Preventive maintenance, Predictive maintenance, 0201 civil engineering, Reliability engineering, [SPI.MAT]Engineering Sciences [physics]/Materials, Maintenance testing, business, Reliability (statistics), ComputingMilieux_MISCELLANEOUS, Degradation (telecommunications)
Abstract

Preventive maintenance allows us to ensure an acceptable level of reliability during the structural lifecycle. A conditional maintenance policy is based on periodic inspections of degradation, which eventually trigger alarms related to repairs and replacements. In practice, however, quantitative knowledge of the state of degradation and operation conditions presents many uncertainties, which leads to a difficult decision-making process. Therefore, reliability-based maintenance becomes mandatory for decision-making.

Published
2012
Full Text
View/download PDF

2. Generic prognosis model for proactive maintenance decision support: application to pre-industrial e-maintenance test bed

Author

Pierre Cocheteux, Alexandre Voisin, Eric Levrat, Benoît Iung, Centre de Recherche en Automatique de Nancy (CRAN), and Université Henri Poincaré - Nancy 1 (UHP)-Institut National Polytechnique de Lorraine (INPL)-Centre National de la Recherche Scientifique (CNRS)

Subjects
0209 industrial biotechnology, Decision support system, Engineering, Business process, Process (engineering), Maintenance, E-maintenance platform, 02 engineering and technology, Industrial and Manufacturing Engineering, [SPI.AUTO]Engineering Sciences [physics]/Automatic, 020901 industrial engineering & automation, Artificial Intelligence, Component (UML), 0202 electrical engineering, electronic engineering, information engineering, E-maintenance, business.industry, Proactivity, Prognosis, Proactive maintenance, MIMOSA, Maintenance testing, Risk analysis (engineering), Anticipation (artificial intelligence), Systems engineering, 020201 artificial intelligence & image processing, business, Software
Abstract

International audience; Proactivity in maintenance, which is mainly materialized by degradation-based anticipation, becomes essential to avoid failure situation with negative impact on product and/or system conditions. It leads to make emerging the E-maintenance philosophy to move from “fail and fix” maintenance practices to “predict and prevent” strategies. Within these new strategies, the anticipation action is fully supported by prognosis business process. Indeed it analyses the degradation impact on the component itself but also on the global performances of the production system in order to predict future failures of the system and investigate (future maintenance) actions. However, only few research works focuses on generic and scalable prognostic approach. Existingmethods are generally restricted on component view and for solving the failure prediction issue. Consequently, the contribution presented in this paper aims at developing a global formalization of the generic prognosis business process. This generic process can be used after, from an instantiation procedure, to develop specific prognosis processes related to particular application such as shown in this paper with the case of E-maintenance platform developed within DYNAMITE Project.

Published
2009
Full Text
View/download PDF

3. Implementing an Automatic Functional Test Pattern Generation for Mixed-Signal Boards in a Maintenance Context

Author

Gilles, Bertrand, Nana, Laurent Tchamnda, Nicolas, Valérie-Anne, Laboratoire d'Informatique des Systèmes Complexes (LISYC), École Nationale d'Ingénieurs de Brest (ENIB)-Université de Brest (UBO)-Institut Brestois du Numérique et des Mathématiques (IBNM), and Université de Brest (UBO)-Université de Brest (UBO)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)

Subjects
automatic test pattern generation, modeling, Maintenance testing, [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], mixed-signal boards
Abstract

International audience; In this paper, we present in the context of mixed-signal board maintenance testing, language and implementation aspects of an automatic functional test pattern generation approach. The goal is to help maintenance test engineers. Our modeling method for mixed-signal boards and their components is presented and the languages proposed for modeling are described. The implementation of our test data generation process based on constraint logic programming is discussed. The application to a simple board is shown and the tool Copernicia developed in the context of our work is presented.

Published
2007

4. Modeling and Generation of Test Patterns for Mixed-Signal Boards: Dealing With Basic Signals

Author

Gilles, Bertrand, Nana, Laurent Tchamnda, Nicolas, Valérie-Anne, Laboratoire d'Informatique des Systèmes Complexes (LISYC), École Nationale d'Ingénieurs de Brest (ENIB)-Université de Brest (UBO)-Institut Brestois du Numérique et des Mathématiques (IBNM), and Université de Brest (UBO)-Université de Brest (UBO)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)

Subjects
maintenance testing, basic signals, modeling, [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], mixed-signal boards
Abstract

International audience; In the context of maintenance testing and diagnosis of faulty boards, a functional FSM (Finite State Machine)-based model for mixed-signal board has been introduced. The board is broken down into interconnected functional blocks. Each block has an associated functional model which describes its behavior and a test model which specifies how the block can be efficiently tested. A test model for a block is created by merging its functional model and a chosen test strategy. The board checking consists in testing each block individually using its test model and functional models of other blocks. Test patterns for a component are generated by covering the transitions of its test model and propagation to primary inputs/outputs through functional models of other blocks. The board test data set is built by using the test patterns for all the blocks of the board. The current improvement of the method deals with basic signals.

Published
2007

5. A Maintenance-Oriented Board testing Approach

Author

Nicolas, Valérie-Anne, Gilles, Bertrand, Lemarchand, Laurent, Castel, Bruno, Laboratoire d'Informatique des Systèmes Complexes (LISYC), École Nationale d'Ingénieurs de Brest (ENIB)-Université de Brest (UBO)-Institut Brestois du Numérique et des Mathématiques (IBNM), Université de Brest (UBO)-Université de Brest (UBO)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne), Lab-STICC_UBO_CACS_MOCS, Université de Brest (UBO)-Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC), École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-Télécom Bretagne-Institut Brestois du Numérique et des Mathématiques (IBNM), Université de Brest (UBO)-Université européenne de Bretagne - European University of Brittany (UEB)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)-Institut Mines-Télécom [Paris] (IMT)-Centre National de la Recherche Scientifique (CNRS)-École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Télécom Bretagne-Institut Brestois du Numérique et des Mathématiques (IBNM), and Université de Brest (UBO)-Université européenne de Bretagne - European University of Brittany (UEB)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)-Institut Mines-Télécom [Paris] (IMT)-Centre National de la Recherche Scientifique (CNRS)

Subjects
modelling, diagnosis, automatic test pattern generation, mixed-signal board testing, Maintenance testing, [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE]
Abstract

International audience; We present an ongoing work in the domain of mixed-signal board maintenance testing, supported by an industrial case study. We propose a method providing a semi-automation and an help for the board maintenance testing and diagnosis stages. It is validated by the implementation of a prototype tool.

Published
2005

6. Maintenance Testing of Mixed-Signal Boards: the FCB case study

Author

Nicolas, Valérie-Anne, Gilles, Bertrand, Lemarchand, Laurent, Marcé, Lionel, Castel, Bruno, Laboratoire d'Informatique des Systèmes Complexes (LISYC), École Nationale d'Ingénieurs de Brest (ENIB)-Université de Brest (UBO)-Institut Brestois du Numérique et des Mathématiques (IBNM), Université de Brest (UBO)-Université de Brest (UBO)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne), Lab-STICC_UBO_CACS_MOCS, Université de Brest (UBO)-Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC), École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-Télécom Bretagne-Institut Brestois du Numérique et des Mathématiques (IBNM), Université de Brest (UBO)-Université européenne de Bretagne - European University of Brittany (UEB)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)-Institut Mines-Télécom [Paris] (IMT)-Centre National de la Recherche Scientifique (CNRS)-École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Télécom Bretagne-Institut Brestois du Numérique et des Mathématiques (IBNM), and Université de Brest (UBO)-Université européenne de Bretagne - European University of Brittany (UEB)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)-Institut Mines-Télécom [Paris] (IMT)-Centre National de la Recherche Scientifique (CNRS)

Subjects
modelling, automatic test pattern generation, diagnosis, mixed-signal board testing, Maintenance testing, [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE]
Abstract

We present an ongoing work in the domain of mixed-signal board maintenance testing, supported by an industrial case study. We propose a method providing a semi-automation and an help for the board maintenance testing and diagnosis stages. It is validated by the implementation of a prototype tool.

Published
2005

7. Efficient UBIST for RAMs

Author

Michael Nicolaidis, iROc Technologies (IROC TECHNOLOGIES), Cadence Connection-EDA Consortium-FSA-Cubic Micro, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)

Subjects
Scheme (programming language), Engineering, 0211 other engineering and technologies, unified-BIST-technique, 02 engineering and technology, Integrated circuit, Hardware_PERFORMANCEANDRELIABILITY, off-line-test, law.invention, law, 0202 electrical engineering, electronic engineering, information engineering, self-checking-implementation, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, computer.programming_language, 021103 operations research, business.industry, concurrent-on-line-testing, fault-coverage, 020202 computer hardware & architecture, Maintenance testing, Built-in self-test, Embedded system, PACS 85.42, Fault coverage, integrated-circuits, business, computer, UBIST, RAMs
Abstract

ISBN: 0818654406; First presents a self-checking implementation for RAMs. Then, the unified BIST technique is applied to this scheme. It merges self-checking and BIST techniques and allows a high fault coverage for all tests needed for integrated circuits, e.g. off-line test (manufacturing and maintenance test) and periodic as well as concurrent on-line testing. In order to preserve the RAM contents for periodic on-line testing the authors employ a transparent BIST implementation.

Published
1994
Full Text
View/download PDF

8. Efficient UBIST implementation for microprocessor sequencing parts

Author

Michael Nicolaidis, iROc Technologies (IROC TECHNOLOGIES), Cadence Connection-EDA Consortium-FSA-Cubic Micro, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)

Subjects
Scheme (programming language), self-checking, Computer science, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Integrated circuit, logic-testing, microprocessor-sequencing-parts, production-testing, Field (computer science), law.invention, law, unified-BIST, 0202 electrical engineering, electronic engineering, information engineering, Overhead (computing), Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, computer.programming_language, Electronic circuit, mentation-for-microprocessor-sequencing, design-verification, Sequential logic, area-overhead, business.industry, fault-coverage, 020208 electrical & electronic engineering, offline-test, self-checking-solution, 020202 computer hardware & architecture, Microprocessor, Maintenance testing, MC-68000-microprocessor, online-concurrent-error-detection, Computer architecture, Built-in self-test, Embedded system, functional-circuits, PACS 85.42, Fault coverage, integrated-circuits, maintenance-test, business, Error detection and correction, UBIST-implementation, computer, Motorola-MC-68000-microprocessor, sequencing
Abstract

ISBN: 081869064X; An improved self-checking solution for the sequencing part of the MC 68000 microprocessor is presented. Compared with previous self-checking schemes for this microprocessor, the present scheme makes its possible to reduce the overhead and simplifies the implementation of both functional circuits, and checkers. The unified BIST (built-in self-test) method is applied to this scheme. This method uses a merging of self-checking and BIST techniques and allows a high fault coverage for all tests needed for integrated circuits, e.g., offline test (design verification, manufacturing, and maintenance test) and online concurrent error detection. An area overhead of about 27% is required, which is quite satisfactory in comparison with previous results.

Published
1990
Full Text
View/download PDF

9. Self-exercising checkers for unified built-in self-test (UBIST)

Author

Michael Nicolaidis, iROc Technologies (IROC TECHNOLOGIES), Cadence Connection-EDA Consortium-FSA-Cubic Micro, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)

Subjects
Mean time between failures, Computer science, internal-test-pattern-generation, 02 engineering and technology, Integrated circuit, law.invention, law, 0202 electrical engineering, electronic engineering, information engineering, Redundancy (engineering), Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, unified-built-in-self-test, business.industry, fault-coverage, 020208 electrical & electronic engineering, offline-test, Fault tolerance, Computer Graphics and Computer-Aided Design, 020202 computer hardware & architecture, Maintenance testing, online-concurrent-error-detection, Built-in self-test, Computer engineering, self-exercising-checkers, Embedded system, PACS 85.42, Fault coverage, integrated-circuits, code-disjoint-property, fault-hypotheses, Error detection and correction, business, Software, UBIST
Abstract

An original built-in self-test (BIST) scheme is proposed aimed at covering some of the shortcomings of self-checking circuits and applicable to all tests needed for integrated circuits. In this scheme, self-checking techniques and built-in self-test techniques are combined in an original way to take advantage of each other. The result is a unified BIST scheme (UBIST), allowing high fault coverage for all tests needed for integrated circuits, e.g., offline test (design verification, manufacturing test, maintenance test) and online concurrent error detection. An important concept introduced is that of self-exercising checkers. The strongly code-disjoint property of the checkers is ensured for a very large class of fault hypotheses by internal test pattern generation, and the design of the checkers is simplified. >

Published
1989
Full Text
View/download PDF

Catalog

Books, media, physical & digital resources
See catalog results