Search

Parallel applications are essential for efficiently using the computational power of a MultiProcessor System-on-Chip (MPSoC). Unfortunately, these applications do not scale effortlessly with the number of cores because of synchronization operations that take away valuable computational time and restrict the parallelization gains. The existing solutions either restrict the application to a subset of synchronization primitives, require refactoring the source code of it, or both. We introduce Subutai, a hardware/software architecture designed to distribute the synchronization mechanisms over the Network-on-Chip. Subutai is comprised of novel hardware specialized in accelerating synchronization operations, a small private memory for recording events, an operating system driver, and a user space custom library that supports legacy and novel parallel applications. We target the POSIX Threads (PThreads) library as it is widely used as a synchronization library, and internally by other libraries such as OpenMP and Threading Building Blocks. We also provide extensions to Subutai intended to further accelerate parallel applications in two scenarios: (i) multiple applications running in a highly-contended scheduling scenario; (ii) remove the access serialization to condition variables in PThreads. Experimental results with four applications from the PARSEC benchmark running on a 64-core MPSoC show an average application speedup of 1.57× compared with the legacy software solutions. The same applications are further sped up to 5% using our proposed Critical Section-aware scheduling policy compared to a baseline Round-Robin scheduler without any changes in the application source code.; Les applications parallèles sont essentielles pour utiliser efficacement la puissance de calcul des systèmes multi-processeurs (MPSoC). Cependant, ces applications ne s’adaptent pas sans effort au nombre de cœurs à cause des opérations de synchronisation qui limitent les gains de parallélisation. Les solutions existantes soit se restreignent à un sous-ensemble de primitives de synchronisation, soit nécessitent de modifier le code source de l'application, ou les deux. Nous présentons Subutai, une solution logiciel/matériel conçue pour distribuer les mécanismes de synchronisation sur le réseau sur puce, tout en restant compatible avec le code source originel. Subutai est composé d’un matériel spécialisé dans l’accélération des opérations de synchronisation, une mémoire privée, un pilote de système d’exploitation et une bibliothèque personnalisée. Nous ciblons la bibliothèque POSIX Threads (PThreads), largement utilisée comme bibliothèque de synchronisation native et en interne par d’autres bibliothèques telles que OpenMP ou TBB. Nous fournissons aussi des extensions à Subutai destinées à accélérer encore davantage les applications dans deux cas: (i) plusieurs applications dans un contexte d'exécution fortement disputé; et (ii) sérialisation d’accès pour les variables condition dans PThreads. Les résultats expérimentaux sur quatre applications du benchmark PARSEC fonctionnant sur un MPSoC à 64 cœurs montrent une accélération moyenne des applications de 1,57× par rapport à des solutions purement logicielles. Une accélération de 5% en plus est obtenue en utilisant notre politique d'ordonnancement Critical Section-aware comparée à un ordonnanceur Round-Robin de base

Parallel applications are essential for efficiently using the computational power of a MultiProcessor System-on-Chip (MPSoC). Unfortunately, these applications do not scale effortlessly with the number of cores because of synchronization operations that take away valuable computational time and restrict the parallelization gains. The existing solutions either restrict the application to a subset of synchronization primitives, require refactoring the source code of it, or both. We introduce Subutai, a hardware/software architecture designed to distribute the synchronization mechanisms over the Network-on-Chip. Subutai is comprised of novel hardware specialized in accelerating synchronization operations, a small private memory for recording events, an operating system driver, and a user space custom library that supports legacy and novel parallel applications. We target the POSIX Threads (PThreads) library as it is widely used as a synchronization library, and internally by other libraries such as OpenMP and Threading Building Blocks. We also provide extensions to Subutai intended to further accelerate parallel applications in two scenarios: (i) multiple applications running in a highly-contended scheduling scenario; (ii) remove the access serialization to condition variables in PThreads. Experimental results with four applications from the PARSEC benchmark running on a 64-core MPSoC show an average application speedup of 1.57× compared with the legacy software solutions. The same applications are further sped up to 5% using our proposed Critical Section-aware scheduling policy compared to a baseline Round-Robin scheduler without any changes in the application source code.; Les applications parallèles sont essentielles pour utiliser efficacement la puissance de calcul des systèmes multi-processeurs (MPSoC). Cependant, ces applications ne s’adaptent pas sans effort au nombre de cœurs à cause des opérations de synchronisation qui limitent les gains de parallélisation. Les solutions existantes soit se restreignent à un sous-ensemble de primitives de synchronisation, soit nécessitent de modifier le code source de l'application, ou les deux. Nous présentons Subutai, une solution logiciel/matériel conçue pour distribuer les mécanismes de synchronisation sur le réseau sur puce, tout en restant compatible avec le code source originel. Subutai est composé d’un matériel spécialisé dans l’accélération des opérations de synchronisation, une mémoire privée, un pilote de système d’exploitation et une bibliothèque personnalisée. Nous ciblons la bibliothèque POSIX Threads (PThreads), largement utilisée comme bibliothèque de synchronisation native et en interne par d’autres bibliothèques telles que OpenMP ou TBB. Nous fournissons aussi des extensions à Subutai destinées à accélérer encore davantage les applications dans deux cas: (i) plusieurs applications dans un contexte d'exécution fortement disputé; et (ii) sérialisation d’accès pour les variables condition dans PThreads. Les résultats expérimentaux sur quatre applications du benchmark PARSEC fonctionnant sur un MPSoC à 64 cœurs montrent une accélération moyenne des applications de 1,57× par rapport à des solutions purement logicielles. Une accélération de 5% en plus est obtenue en utilisant notre politique d'ordonnancement Critical Section-aware comparée à un ordonnanceur Round-Robin de base

International audience; As the System-on-Chip (SoC) complexity increases, hardware/software co-design plays an important role to improve design productivity, reduce time to market, and optimize the overall results. Consequently, there is a high interest in providing rapid system validation in such a paradigm to achieve the aforementioned objectives. There exist in previous works proto-typing techniques related to the development phase. FPGA-based prototyping has the benefits of enabling HW/SW integration and system validation after the Register Transfer Level (RTL) implementation is available while virtual platforms provide capabilities to accelerate software development with higher level functional models, e.g. Transaction Level Modeling (TLM). In this paper, we propose a hybrid prototyping methodology which takes advantage of virtual and FPGA-based prototyping in a single framework. We aim to provide a rapid and flexible system validation solution for HW/SW co-design at various stages of development based on the availability of TLM and RTL implementations. The proposed methodology allows online and offline performance analysis and debugging for early feedback in HW/SW architecture exploration. This was evaluated in the experiments with a neural network processor as a case study.

Mobile devices, at each new release of the standards and following users’ continuous requests of new services, have to support more and more features, which are also becoming more and more demanding from the computational point of view. As a consequence, being able to fulfil new requirements and at the same time to provide power efficient chips is nowadays the most important challenge for mobile devices system designers. To tackle this challenge, novel system level performance and power modeling approaches have been proposed allowing hardware/software (HW/SW) architectures to be explored right at the very first steps of a System-on-Chip (SoC) design flow. However, existing solutions have limited support for the power optimization of the memory system (including SDRAM) that may occupy more than 70% of a chip area and consume more than 30% of the total energy. In our work, we propose a SystemC-TLM-based simulation framework at Electronic System Level (ESL), which is able to support the joint exploration of a SoC architecture and its memory configuration. This new framework helps in optimizing the SoC energy consumption while matching the required performance in terms of power and performance, as well as of memory bandwidth and latency.; Les appareils mobiles, à chaque nouvelle version des normes et suivant les demandes continues de nouveaux services par les utilisateurs, doivent prendre en charge de plus en plus de fonctionnalités, qui deviennent également de plus en plus exigeantes du point de vue informatique. Par conséquent, être en mesure de répondre aux nouvelles exigences tout en fournissant des puces à faible consommation d’énergie est aujourd’hui le défi le plus important pour les concepteurs de systèmes pour appareils mobiles. Pour relever ce défi, de nouvelles approches de modélisation de la performance et de la puissance au niveau système ont été proposées, permettant d'explorer les architectures matérielles/ logicielles (HW / SW) dès les toutes premières étapes d'un flot de conception de systèmes sur puce (SoC). Cependant, les solutions existantes prennent en charge de manière limitée l'optimisation de la puissance du système de mémoire (y compris la mémoire SDRAM), qui peut occuper plus de 70% de la surface d'une puce et consommer plus de 30% de l'énergie totale. Dans nos travaux, nous proposons un cadre de simulation basé sur SystemC-TLM au niveau Electronic System Level (ESL), capable de prendre en charge l’exploration commune d’une architecture SoC et de sa configuration mémoire. Ce nouveau cadre permet d’optimiser la consommation d’énergie des SoC tout en faisant correspondre les performances requises en termes de puissance et de performances, de bande passante mémoire et de temps de latence.

Mobile devices, at each new release of the standards and following users’ continuous requests of new services, have to support more and more features, which are also becoming more and more demanding from the computational point of view. As a consequence, being able to fulfil new requirements and at the same time to provide power efficient chips is nowadays the most important challenge for mobile devices system designers. To tackle this challenge, novel system level performance and power modeling approaches have been proposed allowing hardware/software (HW/SW) architectures to be explored right at the very first steps of a System-on-Chip (SoC) design flow. However, existing solutions have limited support for the power optimization of the memory system (including SDRAM) that may occupy more than 70% of a chip area and consume more than 30% of the total energy. In our work, we propose a SystemC-TLM-based simulation framework at Electronic System Level (ESL), which is able to support the joint exploration of a SoC architecture and its memory configuration. This new framework helps in optimizing the SoC energy consumption while matching the required performance in terms of power and performance, as well as of memory bandwidth and latency.; Les appareils mobiles, à chaque nouvelle version des normes et suivant les demandes continues de nouveaux services par les utilisateurs, doivent prendre en charge de plus en plus de fonctionnalités, qui deviennent également de plus en plus exigeantes du point de vue informatique. Par conséquent, être en mesure de répondre aux nouvelles exigences tout en fournissant des puces à faible consommation d’énergie est aujourd’hui le défi le plus important pour les concepteurs de systèmes pour appareils mobiles. Pour relever ce défi, de nouvelles approches de modélisation de la performance et de la puissance au niveau système ont été proposées, permettant d'explorer les architectures matérielles/ logicielles (HW / SW) dès les toutes premières étapes d'un flot de conception de systèmes sur puce (SoC). Cependant, les solutions existantes prennent en charge de manière limitée l'optimisation de la puissance du système de mémoire (y compris la mémoire SDRAM), qui peut occuper plus de 70% de la surface d'une puce et consommer plus de 30% de l'énergie totale. Dans nos travaux, nous proposons un cadre de simulation basé sur SystemC-TLM au niveau Electronic System Level (ESL), capable de prendre en charge l’exploration commune d’une architecture SoC et de sa configuration mémoire. Ce nouveau cadre permet d’optimiser la consommation d’énergie des SoC tout en faisant correspondre les performances requises en termes de puissance et de performances, de bande passante mémoire et de temps de latence.

International audience; The fast development of quantum computers represents a risk for secure communications. Current traditional public-key cryptography will not withstand attacks performed on quantum computers. In order to prepare for such a quantum threat, electronic systems must integrate efficient and secure post-quantum cryptography which is able to meet the different application requirements and to resist implementation attacks. The NTRU cryptosystem is one of the main candidates for practical implementations of post-quantum public-key cryptography. The standardized version of NTRU (IEEE-1363.1) provides security against a large range of attacks through a special padding scheme. So far, NTRU hardware and software solutions have been proposed. However, the hardware solutions do not include the padding scheme or they use optimized architectures that lead to a degradation of the security level. In addition, NTRU software implementations are flexible but most of the time present a low performance when compared to hardware solutions. In this work, for the first time, we present a hardware/software co-design approach compliant with the IEEE-1363.1 standard. Our solution takes advantage of the flexibility of the software NTRU implementation and the speedup due to the hardware accelerator specially designed in this work. Furthermore, we provide a refined security reduction analysis of an optimized NTRU hardware implementation presented in a previous work.

International audience; Dynamic binary translation is a processor emulation technology that allows to execute in a very efficient manner a binary program for an instruction-set architecture A on a processor having instruction-set architecture B. This chapter starts by giving a rapid overview of the dynamic binary translation process and its peculiarities. Then, it focuses on the support for SIMD instruction and the translation for VLIW architectures, which bring upfront new challenges for this technology. Next, it shows how the translation process can be enhanced by the insertion of instructions to monitor nonfunctional metrics, with the aim of giving, for instance, timing or power consumption estimations. Finally, it details how it can be integrated within virtual prototyping platforms, looking in particular at the synchronization issues.

National audience; An autonomous mobile platform is endowed with a navigational system which must contain multiple functional bricks: perception, localization, path planning and motion control. As soon as such a robot or vehicle moves in a crowded environment, it continously loops several tasks in real time: sending reference values to motors' actuators, calculating its position in respect to a known reference frame and detection of potential obstacles on its path. Thanks to semantic richness provided by images and to low cost of visual sensors, these tasks often exploit visual cues. Other embedded systems running on these mobile platforms thus demand for an additional integration of high-speed embeddable processing systems capable of treating abundant visual sensorial input in real-time. Moreover, constraints influencing the autonomy of the mobile platform impose low power consumption. This thesis proposes SOPC (System on a Programmable Chip) architectures for efficient embedding of vison-based localization and obstacle detection tasks in a navigational pipeline by making use of the software/hardware co-design methodology. The obtained results are equivalent or better in comparison to state-of-the-art for both EKF-SLAM based visual odometry: regarding the local map size management containing seven-dimensional landmarks and model-based detection-by-identification obstacle detection: algorithmic precision over execution speed metric.; Un véhicule autonome ou un robot mobile est équipé d'un système de navigation qui doit comporter plusieurs briques fonctionnelles pour traiter de perception, localisation, planification de trajectoires et locomotion. Dès que ce robot ou ce véhicule se déplace dans un environnement humain dense, il exécute en boucle et en temps réel plusieurs fonctions pour envoyer des consignes aux moteurs, pour calculer sa position vis-à-vis d'un repère de référence connu, et pour détecter de potentiels obstacles sur sa trajectoire; du fait de la richesse sémantique des images et du faible coût des caméras, ces fonctions exploitent souvent la vision. Les systèmes embarqués sur ces machines doivent alors intégrer des cartes assez puissantes pour traiter des données visuelles en temps réel. Par ailleurs, les contraintes d'autonomie de ces plateformes imposent de très faibles consommations énergétiques. Cette thèse proposent des architectures de type SOPC (System on Programmable Chip) conçues par une méthodologie de co-design matériel/logiciel pour exécuter de manière efficace les fonctions de localisation et de détection des obstacles à partir de la vision. Les résultats obtenus sont équivalents ou meilleurs que l'état de l'art, concernant la gestion de la carte locale d'amers pour l'odométrie-visuelle par une approche EKF-SLAM, et le rapport vitesse d'exécution sur précision pour ce qui est de la détection d'obstacles par identification dans les images d'objets (piétons, voitures...) sur la base de modèles appris au préalable.

ISBN : 978-1-4673-3029-9; International audience; We introduce a static binary translation flow in native simulation context for cross-compiled VLIW executables. This approach is interesting in situations where either the source code is not available or the target platform is not supported by any retargetable compilation framework, which is usually the case for VLIW processors. The generated simulators execute on a Hardware-Assisted Virtualization (HAV) based native platform. We have implemented this approach for a TI C6x series processor and our simulation results show a speed-up of around two orders of magnitude compared to the cycle accurate simulators.

International audience; In this article, we present two studies that pave the way towards a mobile implementation of the WAAVES certified medical image compression encoder. On the algorithmic side, we compared three techniques to increase the compression rate. The obtained results show a significant bit-rate reduction, around 40% with respect to the WAAVES encoder, while keeping the same visual quality. On the architectural side, we describe the HW/SW co-design of an architecture implemented in a FPGA platform. By using code profiling, critical portions of the code were identified, then two methods for hardware acceleration were used to implement the critical part of the coder. The tests were done on a StratixIVGX230 FPGA and the results showed that HW/SW co-design could achieve up to 20x performance gain in the critical portion. The combination of these results demonstrates the feasibility of a mobile implementation of the WAAVES certified medical image coder suitable for e-health applications.

Hardware/software (HW/SW) Co-development techniques exploits the trade-offs between hardware and software in a system through their parallel design, taking advantage of the flexibility of the system design to develop architectures that can meet stringent timing and performance requirements with a shorter design cycle. Advances in the automation of the design of HW and SW, the adoption of the Model Driven Architecture (MDA) paradigm and Component-Based techniques make possible the definition of a proper integration substrate that facilitates the continuous interaction of the HW and SW development paths.

Electronic Chips & Systems Design Languagesoutlines and describes the latest advances in design languages. The challenge of System on a Chip (SOC) design requires designers to work in a multi-lingual environment which is becoming increasingly difficult to master. It is therefore crucial for them to learn, almost in real time, from the experiences of their colleagues in the use of design languages and how these languages have become more advanced to cope with system design. System designers, as well as students willing to become system designers, often do not have the time to attend all scientific events where they could learn the necessary information. This book will bring them a selected digest of the best contributions and industry strength case studies. All the levels of abstraction that are relevant, from the informal user requirements down to the implementation specifications, are addressed by different contributors. The author, together with colleague authors who provide valuable additional experience, presents examples of actual industrial world applications. Furthermore the academic concepts presented in this book provide excellent theories to student readers and the concepts described are up to date and in so doing provide most suitable root information for Ph.D. postgraduates.

In the present document the idea of building around the SIGNAL language and its environment, a methodology for the evaluation of implementation alternatives, design space exploration and implementation of R/T systems, is investigated. The driving force behind this effort is the desire to exploit the advantage SIGNAL in the domain of functional specification, as well as the numerous tools built around it. A Real-Time co-design methodology is proposed and the basic tools that will assist the user in the development process, are described. Such a methodology intends to bridge the existing gap in the SIGNAL environment between specification and actual implementation.