Search

International audience; In this work, we propose a new method for detecting ring oscillators characterized by combinatorial loops. These circuits are currently undetected by conventional bitstream analysis tools, all of which are based on reverse engineering. We analyze the bitstream from a semantic point of view and propose a two-dimensional model (image). The model allows us to identify features related to the presence of ring oscillators in the FPGA bitstream image. A proof-of-concept is demonstrated on the Stratix-IV-like FPGA architecture.; Dans ce travail nous proposons une nouvelle méthode de détection d'oscillateurs en anneau, caractérisé par des boucles combinatoires. Ces circuits sont actuellement non détecté par les outils conventionnels d'analyse de bitstream tous basés sur l'ingénierie inversée. Nous analysons le bitstream d'un point de vue sémantique et proposons un modèle bidimensionnel (image). Le modèle nous permet d'identifier des caractéristiques liées à la présence d'oscillateurs en anneaux dans l'image du bitstream du FPGA. Une preuve de faisabilité est démontrée sur l'architecture FPGA Stratix-IV-like.

This thesis has been realized in Télécom Paris and it has been financed by Nokia Bell Labs France. It founds its motivations in the increasing usage of hardware accelerators such as FPGAs and their recent integration in modern cloud data center [1][2]. In some cases, servers and FPGAs are rented to users and the cost is related to the utilization time. Thus, offering a better sharing of FPGA pools would interest all stakeholders, namely cloud providers and users. We focus on scheduling and, in particular, we focus on makespan minimization of applications. The latter are assumed to be composed of several dependent tasks, whose features (i.e., dependencies, execution time, resource requirements, and so on) are known prior to their execution. With respect to the state of the art, we have sought to design an approach which is, at the same time, (i) general, (ii) fast and (iii) of high-quality. Indeed, several related works represent the applications and the architecture through simple models (e.g., the FPGA is often represented only with the amount of reconfigurable logic). We retain that such simple models may lead to unfeasible scheduling. Moreover, the vast majority of them is either based on slow and precise algorithms or on fast heuristics whose quality is far from the optimum. We therefore propose a scheduling solution [3] characterized by a good quality in terms of makespan while keeping the decision time in the order of tens of milliseconds for common applications. The main contributions of the thesis are a modelling proposal for FPGAs, the design of a heuristic which targets the makespan minimization and the evaluation of this heuristic on a synthetic benchmark of pseudo-randomly generated applications. Additionally, we have integrated this method to a model-driven engineering (MDE) tool to better support the early design of embedded systems. Finally, we propose several extensions to extend the approach to different architectures.References:[1] A. M. Caulfield et al., "A cloud-scale acceleration architecture," 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Taipei, 2016, pp. 1-13, doi: 10.1109/MICRO.2016.7783710[2] Amazon Web Services Elastic Compute Cloud, https://docs.aws.amazon.com/ec2/index.html?nc2=h_ql_doc_ec2[3] Matteo Bertolino, Andrea Enrici, Renaud Pacalet, Ludovic Apvrille. Efficient Scheduling of FPGAs for Cloud Data Center Infrastructures. Euromicro DSD 2020, Aug 2020, Portorož, Slovenia. Proceedings will be published on IEEExplore, paper available on HAL of Télécom Paris: https://hal.telecom-paris.fr/hal-02894662v1; Cette thèse a été faite à Télécom Paris et a été financée par Nokia Bell Labs France. Les contributions de la thèse trouvent leur motivation d'une part dans l'usage croissant d'accélérateurs matériel, comme les FPGAs pour décharger les processeurs de fonctions complexes. D'autre part, ces accélérateurs sont de plus en plus intégrés dans des centre de calculs ("cloud") [1][2]. Ces FPGAs peuvent être loués aux utilisateurs, et leur coût d'utilisation dépend alors de la durée allouée. Ainsi, il devient intéressant de mettre en place des techniques permettant de minimiser le temps d'exécution des applications. Dans cette thèse, nous considérons des applications "flots de données", c'est à dire qu'une tâche attend des données d'une tâche précédente avant de s'exécuter, et produit des données en sortie qui sont utilisées en entrée d'autres tâches. Nous prenons aussi comme hypothèse que ces applications sont pré-caractérisées par leur temps d'exécution sur FPGA ainsi que par les éléments matériels dont elles ont un besoin exclusif sur le FPGA (par exemple : les éléments logiques). Il existe déjà des travaux pour choisir un bon ordonnancement de tâches sur FPGA. Malheureusement, ces derniers utilisent une recherche exhaustive de la meilleur solution, ce qui est très coûteux en temps de calcul, soit ils reposent sur des heuristiques rapides mais dont la solution produite en en règle générale assez éloignée de la solution optimale. De nombreux travaux considèrent aussi des modèles de FPGA trop abstraits : par exemple, le FPGA est modélisé uniquement sous la forme d'un ensemble d'éléments logiques, omettant par exemple les DSPs intégrés aux FPGAs, rendant ainsi la solution calculée éventuellement non utilisable sur un FPGA (concret).La solution que nous proposons dans notre thèse repose sur une modélisation plus réaliste des FPGAs et sur une nouvelle heuristique d'ordonnancement. Cette dernière est itérative sur le graphe : elle extrait du graphe de tâches la tâche les plus complexes en termes de temps de calcul, puis utilise un système d'évaluation pour identifier les tâches les plus pertinentes à grouper avec la tâche la plus complexe. Notre évaluation effectuée sur un grand nombre de graphes d'applications fictives montre que notre heuristique est tout aussi rapide qu'une autre heuristique de référence, tout en offrant de meilleurs résultats. De plus, notre contribution a été intégrée à un environnement orienté modèles pour la conception de systèmes embarqués. De plus, nous dressons des perspectives intéressants pour l'utilisation de notre heuristique dans d'autres contextes.Références:[1] A. M. Caulfield et al., "A cloud-scale acceleration architecture," 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Taipei, 2016, pp. 1-13, doi: 10.1109/MICRO.2016.7783710[2] Amazon Web Services Elastic Compute Cloud, https://docs.aws.amazon.com/ec2/index.html?nc2=h_ql_doc_ec2[3] Matteo Bertolino, Andrea Enrici, Renaud Pacalet, Ludovic Apvrille. Efficient Scheduling of FPGAs for Cloud Data Center Infrastructures. Euromicro DSD 2020, Aug 2020, Portorož, Slovenia. Proceedings will be published on IEEExplore, paper available on HAL of Télécom Paris: https://hal.telecom-paris.fr/hal-02894662v1

International audience; Dataflow languages are widely used for programming real-time embedded systems. They offer high level abstraction above hardware, and are amenable to program analysis and optimisation. This paper addresses the challenge of verifying parallel program transformations in the context of dynamic dataflow models, where the scheduling behaviour and the amount of data each actor computes may depend on values only known at runtime.We present a Linear Temporal Logic (LTL) model checking approach to verify a dataflow program transformation, using three LTL properties to identify cyclostatic actors in dynamic dataflow programs. The workflow abstracts dataflow actor code to Fiacre specifications to search for counterexamples of the LTL properties using the Tina model checker. We also present a new refactoring tool for the Orcc dataflow programming environment, which applies the parallelising transformation to cyclostatic actors. Parallel refactoring using verified transformations speedily improves FPGA performance, e.g.15.4 × speedup with 16 actors.

The increase in both size and diversity of applications regarding modern networks is making traditional computing architectures limited. Indeed, purely software architectures can not sustain typical throughputs, while purely hardware ones severely lack the flexibility needed to adapt to the diversity of applications. Thus, the investigation of programmable hardware, such as Field Programmable Gate Arrays (FPGAs), has been done. These architectures are indeed usually considered as a good tradeoff between performance and flexibility, mainly thanks to the Dynamic Partial Reconfiguration (DPR), which allows to reconfigure a part of the design during run-time.However, this technique can have several drawbacks, especially regarding the storing of the configuration files, called bitstreams. To solve this issue, bitstream relocation can be deployed, which allows to decrease the number of configuration files required. However, this technique is long, error-prone, and requires specific knowledge inFPGAs. A fully automated design flow has been developped to ease the use of this technique. In order to provide flexibility regarding the sequence of treatments to be done on our architecture, a flexible and high-throughput communication structure is required. Thus, a Network-on-Chips study and characterization has been done accordingly to network processing and bitstream relocation properties. Finally, a case study has been developed in order to validate our approach.; L’augmentation de la taille des réseaux actuels ainsi que de la diversité des applications qui les utilisent font que les architectures de calcul traditionnelles deviennent limitées. En effet, les architectures purement logicielles ne permettent pas de tenir les débits en jeu, tandis que celles purement matérielles n’offrent pas assez de flexibilité pour répondre à la diversité des applications. Ainsi, l’utilisation de solutions de type matériel programmable, en particulier les Field Programmable Gate Arrays (FPGAs), a été envisagée. En effet, ces architectures sont souvent considérées comme un bon compromis entre performances et flexibilité, notamment grâce à la technique de Reconfiguration Dynamique Partielle (RDP), qui permet de modifier le comportement d’une partie du circuit pendant l’exécution. Cependant, cette technique peut présenter des inconvénients lorsqu’elle est utilisée de manière intensive, en particulier au niveau du stockage des fichiers de configuration, appelés bitstreams. Pour palier ce problème, il est possible d’utiliser la relocation de bitstreams, permettant de réduire le nombre de fichiers de configuration. Cependant cette technique est fastidieuse et exige des connaissances pointues dans les FPGAs. Un flot de conception entièrement automatisé a donc été développé dans le but de simplifier son utilisation.Pour permettre une flexibilité sur l’enchaînement des traitements effectués, une architecture de communication flexible supportant des hauts débits est également nécessaire. Ainsi, l’étude de Network-on-Chips dédiés aux circuits reconfigurables et au traitements réseaux à haut débit.Enfin, un cas d’étude a été mené pour valider notre approche.

The increase in both size and diversity of applications regarding modern networks is making traditional computing architectures limited. Indeed, purely software architectures can not sustain typical throughputs, while purely hardware ones severely lack the flexibility needed to adapt to the diversity of applications. Thus, the investigation of programmable hardware, such as Field Programmable Gate Arrays (FPGAs), has been done. These architectures are indeed usually considered as a good tradeoff between performance and flexibility, mainly thanks to the Dynamic Partial Reconfiguration (DPR), which allows to reconfigure a part of the design during run-time.However, this technique can have several drawbacks, especially regarding the storing of the configuration files, called bitstreams. To solve this issue, bitstream relocation can be deployed, which allows to decrease the number of configuration files required. However, this technique is long, error-prone, and requires specific knowledge inFPGAs. A fully automated design flow has been developped to ease the use of this technique. In order to provide flexibility regarding the sequence of treatments to be done on our architecture, a flexible and high-throughput communication structure is required. Thus, a Network-on-Chips study and characterization has been done accordingly to network processing and bitstream relocation properties. Finally, a case study has been developed in order to validate our approach.; L’augmentation de la taille des réseaux actuels ainsi que de la diversité des applications qui les utilisent font que les architectures de calcul traditionnelles deviennent limitées. En effet, les architectures purement logicielles ne permettent pas de tenir les débits en jeu, tandis que celles purement matérielles n’offrent pas assez de flexibilité pour répondre à la diversité des applications. Ainsi, l’utilisation de solutions de type matériel programmable, en particulier les Field Programmable Gate Arrays (FPGAs), a été envisagée. En effet, ces architectures sont souvent considérées comme un bon compromis entre performances et flexibilité, notamment grâce à la technique de Reconfiguration Dynamique Partielle (RDP), qui permet de modifier le comportement d’une partie du circuit pendant l’exécution. Cependant, cette technique peut présenter des inconvénients lorsqu’elle est utilisée de manière intensive, en particulier au niveau du stockage des fichiers de configuration, appelés bitstreams. Pour palier ce problème, il est possible d’utiliser la relocation de bitstreams, permettant de réduire le nombre de fichiers de configuration. Cependant cette technique est fastidieuse et exige des connaissances pointues dans les FPGAs. Un flot de conception entièrement automatisé a donc été développé dans le but de simplifier son utilisation.Pour permettre une flexibilité sur l’enchaînement des traitements effectués, une architecture de communication flexible supportant des hauts débits est également nécessaire. Ainsi, l’étude de Network-on-Chips dédiés aux circuits reconfigurables et au traitements réseaux à haut débit.Enfin, un cas d’étude a été mené pour valider notre approche.

International audience; A fully pipelined hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity coming with this module and to accelerate the concerned calculations. Two reconfigurable structures are developed in this paper, the first one concerns angular modes and is identified as Processing Element for Angular (PEA) modes, the other is made in order to handle with the Planar mode and is identified as Processing Element for the Planar (PEP) mode. Each structure is repeated in five paths, that our architecture composed of, working in parallel way. This architecture supports all intra prediction modes for all prediction unit sizes. The synthesis results show that our design can run at 219 MHz for Xilinx Virtex 6 and is capable to process real time 110 1080p frames per second or 24 4K frames per second. (C) 2015 Elsevier B.V. All rights reserved.

International audience; A novel hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity within this standard and to accelerate the concerned calculations. We propose a new pipelined structure that we called Processing Element (PE) to execute all angular modes, and we repeat it in five paths that our architecture composed of. We present also another structure to carry out the Planar mode. This architecture supports all intra prediction modes for all prediction unit sizes. The synthesis results show that our design can run at 213 MHz for Xilinx Virtex 6 and is capable to process real time 120 1080p FPS or 30 4K FPS. To the best of our knowledge, it outperforms all hardware solutions existing in the literature.

International audience; For a standalone Fall Detection system based on computer vision we want to obtain a low power architecture to meet the real time processing, power consumption, energy constraints which also satisfy the high performance in recognition, and accuracy. In this paper, we present the different architecture explorations for Fall Detection system implemented on heterogeneous platform as Zynq-7000 AP SoC platform. We extract the power models based on measurement to have more accuracy for Fall Detection system. The estimation of execution time was taking on Pcore processor like ARM Cortex A9 to find out the candidate for accelerating on Hardware (FPGAs) implementation. Then we analyze the features of power consumption, frame rate, and energy to get the best compromise architecture for standalone Fall Detection system.

International audience; Recently, techniques have been invented to combine encryption and authen- tication into a single algorithm which is called Authenticated Encryption (AE). Combining these two security services in hardware produces smaller area compared to two separate algorithms. AE is implemented in the static part of the FPGA (FPGA silicon) in order to secure the recon guration process to ensure the con dentiality and integrity of the bitstream. Also, it is used in the recon gurable part of the FPGA to support applications which need security requirements like Virtual Private Networks (VPNs). This paper presents two di erent directions for implementing AE cores on FPGAs. First, we present e cient ASIC implementations of AE algorithms, Counter with Cipher Block Chaining Mode (CCM) and Galois Counter Mode (GCM), which are used in the static part of the FPGA in order to secure the recon guration process. Our focus on state of the art algorithms for e cient implementations leads to propose e cient compact architectures in order to be used for FPGA bitstream security. Presented ASIC architectures were evaluated by using 90 and 130 nm technologies. Second, high-throughput GCM architectures are implemented in the recon gurable part of the FPGA by taking the advantage of slow changing key environments like VPNs and embedded memory protection. The proposed architectures were evaluated using Virtex5 and Virtex4 FPGAs. It is shown that the performance of the presented work outperforms the previously reported ones.

International audience; This paper proposes an efficient method for implementing parallel AES-GCM cores using FPGAs. The proposed method improves the performance of the parallel architecture (Throughput/Slice). Presented architectures can be used for applications which require encryption and authentication with slow changing keys like Virtual Private Networks (VPNs). Our architectures were evaluated using Virtex5 FPGAs. It is shown that the performance of the presented parallel AES-GCM architecture outperforms the previously reported ones.

International audience; Since its acceptance as the adopted authenticated encryption algorithm, AES-GCM has been utilized in various security-constrained applications. This paper describes the benefits of adding key-synthesized property to AES-GCM using FPGAs. Presented architectures can be used for applications which require encryption and authentication with slow changing keys like Virtual Private Networks (VPNs). Three methods are selected to implement the SubBytes of AES to increase the flexibility of the presented work. Furthermore, we propose a protocol to protect the bitstream of the proposed architectures. Our architectures were evaluated using Virtex5 and Virtex4 FPGAs. It is shown that the performance of the presented AES-GCM architectures outperforms the previously reported ones.

International audience; In this article, we present two studies that pave the way towards a mobile implementation of the WAAVES certified medical image compression encoder. On the algorithmic side, we compared three techniques to increase the compression rate. The obtained results show a significant bit-rate reduction, around 40% with respect to the WAAVES encoder, while keeping the same visual quality. On the architectural side, we describe the HW/SW co-design of an architecture implemented in a FPGA platform. By using code profiling, critical portions of the code were identified, then two methods for hardware acceleration were used to implement the critical part of the coder. The tests were done on a StratixIVGX230 FPGA and the results showed that HW/SW co-design could achieve up to 20x performance gain in the critical portion. The combination of these results demonstrates the feasibility of a mobile implementation of the WAAVES certified medical image coder suitable for e-health applications.

ISBN 978-1-4673-1206-6; International audience; Soft errors in the configuration memory of SRAM-based FPGAs cause significant and remanent application disturbances. Typical mitigation techniques induce large overheads in terms of resource usage and power consumption. We propose a new approach achieving efficient trade-offs between robustness and overheads, applied to the internal architecture of commercial AT40K devices.

International audience; The possibility of implementing computers in FPGAs, known in the litterature as "Soft Computers", open large teaching oportunities in the domain of parallel architectures. This paper describes the implementation of a SISD computer and its evolution towards a SIMD, in a FPGA platform.

The works presented in this dissertation are carried out in the context of System-on-Chip (SoC) and embedded system design, particularly dedicated to the domain of dynamic reconfiguration related to these complex systems. We present a design flow based on Model Driven Engineering (MDE) and the MARTE SoC Co-Design profile, to specify and implement these SoCs; in order to elevate the abstraction levels and to decrease system complexity. The first contribution related to this thesis is identifying parts of dynamically reconfigurable SoCs that can be modeled at the high abstraction levels. This thesis targets the high level application models to be treated as dynamically swapple regions of a reconfigurable SoC, and proposes generic control models for managing these regions during runtime execution. While these semantics can be introduced at several high abstraction levels of a SoC Co-Design framework, we specially emphasis on fusion at the deployment level, that links intellectual properties to the modeled high level design components. Additionally, these concepts have been integrated into the MARTE metamodel to provide a suitable extension for expressing reconfigurability features at the high level modeling. The second contribution is the proposal of an intermediate metamodel, that isolates the concepts present at the RTL. This metamodel integrates concepts responsible for the hardware execution of the modeled applications, and enriches the control semantics, resulting in creation of a dynamically reconfigurable hardware accelerator with several available implementations. Finally, using the MDE model transformations, we are able to generate HDL code equivalent to the different implementations of the reconfigurable accelerator as well as C langauge source code related to the reconfiguration controller responsible for the switching between the different implementations. Finally, our design flow was verified successfully in a case study related to an anti-collision radar detection system. A key integral component of this system was modeled using the extended MARTE specifications and the generated code was used in the conception and implementation of a dynamically reconfigurable FPGA based SoC.; Les travaux présentés dans cette thèse sont effectuées dans le cadre des Systèmes sur puce (SoC, Systemon Chip) et la conception de systèmes embarqués en temps réel, notamment dédiés au domaine de la reconfiguration dynamique, liés à ces systèmes complexes. Dans ce travail, nous présentons un nouveau flot de conception basé sur l'Ingénierie Dirigée par les Modèles (IDM/MDE) et le profilMARTE pour la conception conjointe du SoC, la spécification et la mise en oeuvre de ces systèmes sur puce reconfigurables, afin d'élever les niveaux d'abstraction et de réduire la complexité du système. La première contribution relative à cette thèse est l'identification des parties de systèmes sur puce reconfigurable dynamiquement qui peuvent être modélisées au niveau d'abstraction élevé. Cette thèse adapte une approche dirigée par l'application et cible les modèles d'application de haut niveau pour être traités comme des régions dynamiques des SoCs reconfigurables. Nous proposons aussi des modèles de contrôle générique pour la gestion de ces régions au cours de l'exécution en temps réel. Bien que cette sémantique puisse être introduite à différents niveaux d'abstraction d'un environnent pour la conception conjointe du SoC, nous insistons tout particulièrement sur sa fusion au niveau du déploiement, qui relie la propriété intellectuelle avec les éléments modélisés à haut niveau de conception. En outre, ces concepts ont été intégrés dans le méta-modèleMARTE et le profil correspondant afin de fournir une extension adéquate pour exprimer les caractéristiques de reconfiguration à la modélisation de haut niveau. La seconde contribution est la proposition d'un méta-modèle intermédiaire, qui isole les concepts présents au niveau transfert de registre (RTL-Register Transfer Level). Ce méta-modèle intègre les concepts chargés de l'exécution matérielle des applications modélisées, tout en enrichissant la sémantique de contrôle, provoquant la création d'un accélérateur matériel reconfigurable dynamiquement avec plusieurs implémentations disponibles. Enfin, en utilisant les transformations de modèlesMDE et les principes correspondants, nous sommes en mesure de générer des codeHDL équivalents à différentes implémentations de l'accélérateur reconfigurable ainsi que différents codes source en langage C/C++ liés au contrôleur de reconfiguration, qui est finalement responsable de la commutation entre les différentes mplémentations. Enfin, notre flot de conception a été vérifié avec succès dans une étude de cas liée à un système anti-radar de détection de collision. Une composante clé intégrante de ce système a été modélisée en utilisant les spécifications MARTE étendu et le code généré a été utilisé dans la conception et la mise en oeuvre d'un SoC sur un FPGA reconfigurable dynamiquement.

International audience; The interest for SRAM based FPGAs has increased in the last few years in embedded systems, due to cost and reconfigurability motivations. Such systems may operate in harsh environments with for example ionizing radiations, and the application may require a high level of dependability. When the FPGAs are not developed on radiation-hardened technologies, using them in critical applications requires evaluating the consequences of modifications in their configuration. This paper summarizes an approach to evaluate at design time the criticality of the various bits in the configuration file of such a FPGA. Results are given on an Atmel component and comparisons are made with experimental results based on laser fault injections and proton ground tests.

National audience; The interest for SRAM based FPGAs has increased in the last few years in embedded systems, due to cost and reconfigurability motivations. Such systems may operate in harsh environments with for example ionizing radiations, and the application may require a high level of dependability. When the FPGAs are not developed on radiation-hardened technologies, using them in critical applications requires evaluating the criticality of modifications in their configuration. This paper summarizes an approach to evaluate at design time the criticality of the various bits in the configuration file of such a FPGA. It is illustrated with some results on an Atmel component

ISBN 978-1-60558-478-2; International audience

System-on-Chip (SoC) can be considered as a particular case of embedded systems and has rapidly became a de-facto solution for implement- ing these complex systems. However, due to the continuous exponential rise in SoC's design complexity, there is a critical need to find new seamless method- ologies and tools to handle the SoC co-design aspects. This paper addresses this issue and proposes a novel SoC co-design methodology based on Model Driven Engineering (MDE) and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard proposed by OMG (Object Management Group), in order to raise the design abstraction levels. Extensions of this standard have enabled us to move from high level specifications to execution platforms such as reconfigurable FPGAs; and allow to implement the notion of Partial Dy- namic Reconfiguration supported by current FPGAs. The overall objective is to carry out system modeling at a high abstraction level expressed in UML (Unified Modeling Language); and afterwards, transform these high level mod- els into detailed enriched lower level models in order to automatically generate the necessary code for final FPGA synthesis.

ISBN : 978-2-84813-124-5; International audience; This paper summarizes the main types of attacks that can be targeted towards secured circuits, with a special emphasis on fault-based attacks (glitch based and laser based). Experimental set-ups are presented and the error patterns induced on a Virtex II FPGA platform are shown. The type of errors induced by lasers in the configuration memory are more specifically analyzed.

International audience; Random number generators are one of basic cryptographic primitives used in cryptographic protocols. Most of true random number generators in Field Programmable Gate Arrays (FPGAs) employ the timing jitter from ring oscillator clocks as a source of randomness. The paper analyses the jitter generated in ring oscillators and it uses a simple physical model of jitter sources to show that the random jitter accumulates slower than the global and manipulable deterministic jitter. This fact, which can be used to attack generators, is not considered even in most recent designs considered to be secure. The paper proposes simple but efficient countermeasure against these attacks. The method is validated using the proposed behavioral VHDL model and it is shown to be efficient in hardware, too.

International audience; We present evaluation of various True Random Number Generator (TRNG) designs implemented in recent Actel Fusion Flash FPGAs. Experiments were focused in both PLL based TRNG and ring oscillators which are the base of many TRNGs. Design of the PLL based TRNG use on-chip free running RC oscillator as clock input. Quality of output random numbers was evaluated by means of NIST statistical test suite for first time in such configuration. The USB interconnection was used for real-time high-speed random numbers download to the computer. Second part of experiments was focused on observation of ring oscillators' influence between each other depending on their mutual position inside the FPGA. The simple cryptographic system was created in Actel ARM enabled Fusion Flash FPGA. The system employs basic cryptographic primitives implemented in CoreMP7 soft-core for pointing out the benefits of this FPGA family for cryptographic purposes.

International audience; Many true random number generators in Field Programmable Gate Arrays (FPGAs) employ the timing jitter from ring oscillator clocks as a source of randomness. In this presentation we are focusing on the jitter generated in ring oscillators. We use a simple physical model of jitter sources to show that the random jitter accumulates slower than the global and manipulable deterministic jitter. This fact, which can be used to attack generators, is not considered even in most recent designs considered to be secure. We propose simple but efficient countermeasure against these attacks. The method is validated using the proposed behavioral VHDL model and it is shown to be efficient in hardware, too.

International audience; State of the art

Special Issue on 18th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis Bordeaux, France, 08-12 October 2007 Edited by Nathalie Labat and André Touboul; International audience; The reconfigurability of SRAM-based FPGAs has also some drawbacks, especially when used in systems requiring a high level of safety and/or dependability. Dealing with single-event effects is an important issue in these systems. This paper presents a software tool to analyze a bit-stream and the functional effects of errors in it. Results of analyses are

International audience

Since the introduction of public key cryptography, the problem of factoring large composites has been of increased interest. The security of the most popular asymmetric cryptographic scheme RSA depends on the hardness of factoring large numbers. The best known method for factoring large integers is the general number field sieve (GNFS). One important step within the GNFS is the factorisation of mid-size numbers for smoothness testing, an efficient algorithm for which is the elliptic curve method (ECM). Since smoothness testing is also suitable for parallelisation, the implementation of ECM in hardware is promising. We show that massive parallel and cost-efficient ECM hardware engines can improve the area–time product of the RSA moduli factorisation via the GNFS considerably. The computation of ECM is a classic example of an algorithm that can be significantly accelerated through special-purpose hardware. The authors thoroughly analyse the prerequisites for an area–time efficient hardware architecture for ECM. The authors present an implementation of ECM to factor numbers up to 200 bits, which is also scalable to other bit lengths. ECM is realised as a software–hardware co-design on a field-programmable gate array (FPGA) and an embedded microcontroller (system-on-chip). Furthermore, the authors provide estimates for state-of-the-art CMOS implementation of the design and for the application of massive parallel ECM engines to the GNFS. This appears to be the first publication of a realised hardware implementation of ECM, and the first description of GNFS acceleration through hardware-based ECM.

A significant factor in the evolution of modern electronic systems is the appearance of new architectures based on the programming of hardware components such as Field programmable Gate Arrays (FPGAs). The introduction of those components as an alternative computation unit and the flexibility they offer increase the interest of suche an integration solution. Moreover, the recent evolutions of the different families allow today the implementation of complex systems with higher constraints on performances. Few works focus on the estimation of an application on a technology of this type. Until now, researchers mainly carried their efforts on the imrpovement of reconfigurable architectures in order to make them powerful and thus to constitute an alternative to ASICs (Application Specific Integrated Circuits). The objective of the work presented in this thesis is to propose techniques and tools associated on programmable architectures. The developed method is generic (it can be applied to several FPGA families) and is located at the behavioral level. It allows the browsing of several architectural solutions and is integrated in a hardware : software codesign methodology.; Un facteur important dans l'évolution des systèmes électroniques modernes est l'apparition de nouvelles architectures basées sur la programmation de circuits matériels tels que les composants programmables. Les récentes évolutions des différentes familles autorisent aujourd'hui l'intégration de systèmes de plus en plus complexes avec des contraintes de performances de plus en plus fortes. D'autre part, la flexibilité offerte par ce type de technologie fait des FPGAs (Field programmable gate arrays) une cible architecturale promise à un bel avenir. L'évaluation des performances d'une application sur une technologie reconfigurable est un problème peu étudié à ce jour. Jusqu'à présent, les chercheurs ont principalement porté leurs efforts sur l'amélioration des architectures afin de les rendre plus performantes et ainsi constituer une réelle alternative aux ASICs (Application specific integrated circuits). L'objectif du travail présenté dans ce mémoire consiste à proposer des techniques et les outils associés permettant l'évaluation rapide des performances (temps, surface) d'applications sur des architectures programmables. La méthode développée est générique (elle s'applique à plusieurs familles de FPGAs) et se situe au niveau comportemental. Elle permet l'exploration de plusieurs solutions architecturales et s'intègre dans un flot de conception conjointe logiciel / matériel.

Neural network hardware implementations have to reconcile simple hardware topologies with often complex neural architectures. Field programmable neural arrays (FPNA) are defined for that. Their computation scheme creates numerous virtual neural links by means of a limited set of communication links, whatever the device, the arithmetic, and the neural structure. Their concrete use has proved that they allow to have the computation power of standard neural models with a reduced set of neural resources easy to map directly to digital hardware. A simple pattern classification problem is chosen in this paper so as to show how FPNA allow to replace complex standard neural architectures by hardware-friendly neural structures. FPNA have been applied to numerous other problems with similar benefits. They are now applied to high-dimensional real-world applications, such as multiband speech recognition.

Article dans revue scientifique avec comité de lecture.; Neural networks are usually considered as naturally parallel computing models. But the number of operators and the complex connection graph of standard neural models can not be directly handled by digital hardware devices. More particularly, several works show that programmable digital hardware is a real opportunity for flexible hardware implementations of neural networks. And yet many area and topology problems arise when standard neural models are implemented onto programmable circuits such as FPGAs, so that the fast FPGA technology improvements can not be fully exploited. Therefore neural network hardware implementations need to reconcile simple hardware topologies with complex neural architectures. A theoretical and practical framework called FPNA allows this combination thanks to some principles of configurable hardware that are applied to neural computation: Field Programmable Neural Arrays lead to powerful neural architectures that are easy to map onto FPGAs, thanks to a simplified topology and an original data exchange scheme. This paper shows how FPGAs have led to the definition of the FPNA computation paradigm. Then it shows how FPNAs contribute to current and future FPGA-based neural implementations by solving the general problems that are raised by the implementation of complex neural networks onto FPGAs.

This paper presents a co-synthesis and prototyping environment of mixed hardware/software systems. The approach starts with a high-level C-VHDL specification. This model is refined during the different steps of design to generate an operational prototype which is mapped onto modular and flexible multiprocessor architecture. The combination between the use of existing design tools and the proposed methodology allows to design real-word applications. The environment is used to design a robot arm speed controller. The system uses an algorithm based on fuzzy logic. After some iterations of simulation and synthesis, a prototype is implemented using an architecture composed of software components and hardware components (microprocessor and FPGAs).