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Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Scan chain defects constitute a significant fraction of the overall digital defect universe, and hence it is well justified that scan chain diagnosis has received increasing research attention in recent years. In this paper, we address the problem of scan chain diagnosis for intermittent faults. We show that the conventional scan chain test pattern is likely to miss an intermittent fault, or inaccurately diagnose it. We propose an improved scan chain test pattern which we show to be effective. Subsequently, we demonstrate that the conventional bound calculation algorithm is likely to produce wrong results in the case of an intermittent fault. We propose a new lowerbound calculation method which does generate correct and tight bounds, even for an intermittence probability as low as 10%.

Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Scan chain defects constitute a significant fraction of the overall digital defect universe, and hence it is well justified that scan chain diagnosis has received increasing research attention in recent years. In this paper, we address the problem of scan chain diagnosis for intermittent faults. We show that the conventional scan chain test pattern is likely to miss an intermittent fault, or inaccurately diagnose it. We propose an improved scan chain test pattern which we show to be effective. Subsequently, we demonstrate that the conventional bound calculation algorithm is likely to produce wrong results in the case of an intermittent fault. We propose a new lowerbound calculation method which does generate correct and tight bounds, even for an intermittence probability as low as 10%.

Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Scan chain defects constitute a significant fraction of the overall digital defect universe, and hence it is well justified that scan chain diagnosis has received increasing research attention in recent years. In this paper, we address the problem of scan chain diagnosis for intermittent faults. We show that the conventional scan chain test pattern is likely to miss an intermittent fault, or inaccurately diagnose it. We propose an improved scan chain test pattern which we show to be effective. Subsequently, we demonstrate that the conventional bound calculation algorithm is likely to produce wrong results in the case of an intermittent fault. We propose a new lowerbound calculation method which does generate correct and tight bounds, even for an intermittence probability as low as 10%.

Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Scan chain defects constitute a significant fraction of the overall digital defect universe, and hence it is well justified that scan chain diagnosis has received increasing research attention in recent years. In this paper, we address the problem of scan chain diagnosis for intermittent faults. We show that the conventional scan chain test pattern is likely to miss an intermittent fault, or inaccurately diagnose it. We propose an improved scan chain test pattern which we show to be effective. Subsequently, we demonstrate that the conventional bound calculation algorithm is likely to produce wrong results in the case of an intermittent fault. We propose a new lowerbound calculation method which does generate correct and tight bounds, even for an intermittence probability as low as 10%.

Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Scan chain defects constitute a significant fraction of the overall digital defect universe, and hence it is well justified that scan chain diagnosis has received increasing research attention in recent years. In this paper, we address the problem of scan chain diagnosis for intermittent faults. We show that the conventional scan chain test pattern is likely to miss an intermittent fault, or inaccurately diagnose it. We propose an improved scan chain test pattern which we show to be effective. Subsequently, we demonstrate that the conventional bound calculation algorithm is likely to produce wrong results in the case of an intermittent fault. We propose a new lowerbound calculation method which does generate correct and tight bounds, even for an intermittence probability as low as 10%.

Embedded First-In First-Out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded FIFO module with asynchronous read and write clocks, which is at least a factor two smaller and also faster than SRAM-based and standard-cell-based counterparts. The detection qualities of the FIFO test for both hard and weak resistive shorts and opens have been analyzed by an IFA-like method based on analog simulation. The defect coverage of the initial FIFO test for shorts in the bit-cell matrix has been improved by inclusion of an additional data background and low-voltage testing; for low-resistant shorts, 100% defect coverage is obtained. The defect coverage for opens has been improved by a new test procedure which includes waiting periods.

Complex SOCs areincreasingly tested in a modular fashion, which enables us torecord the yield-per-module. In this paper, we consider theyield-per-module as the pass probability of the module smanufacturing test. We use it to exploit the abort-on-fail featureof ATEs, in order to reduce the expected test application time. Wepresent a model for expected test application time, which obtainsincreasing accuracy due to decreasing granularity of the abortabletest unit. For a given SOC, with a modular test architectureconsisting of wrappers and disjunct TAMs, and for given passprobabilities per module test, we schedule the tests on each TAMsuch that the expected test application time is minimized. Wedescribe two heuristic scheduling approaches, one without and onewith preemption. Experimental results for the ITC 02 SOC TestBenchmarks demonstrate the effectiveness of our approach, as weachieve up to 97% reduction in the expected test application time,without any modification to the SOC or ATE.