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Your search keyword '"Liu, Zao"' showing total 3 results
Start Over Author "Liu, Zao" Publisher escholarship, university of california
3 results on '"Liu, Zao"'

1. Compact thermal modeling for packaged microprocessor design with practical power maps

Author

Liu, Zao, Tan, Sheldon X-D, Wang, Hai, Hua, Yingbo, and Gupta, Ashish

Subjects
Thermal modeling, Nonlinear modeling, Microprocessor, Package, Power map, Computer Hardware, Computer Hardware & Architecture
Abstract

In this paper, we propose a new behavioral thermal modeling technique for high-performance microprocessors at package level. Firstly, the new approach applies the subspace identification method with the consideration of practical power maps with correlated power signals. We show that the input power signal needs to meet an independence requirement to ensure the model predictability and propose an iterative process to build the models with given error bounds. Secondly, we show that thermal systems fundamentally are nonlinear and then propose a piecewise linear (PWL) scheme to deal with nonlinear effects. The experimental results validated the proposed method on a realistic packaged integrated system modeled by the multi-domain/physics commercial tool, COMSOL. The new piecewise linear models can model thermal behaviors over wide temperature ranges or over different thermal boundary convective conditions due to different fan speeds. Further, the PWL modeling technique can lead to much smaller model order without accuracy loss, which translates to significant savings in both the simulation time and the time required to identify the reduced models compared to the simple modeling method by using the high order models. © 2013 Elsevier B.V. All rights reserved.

Published
2014

2. Compact thermal modeling for package design with practical power maps

Author

Liu, Zao, Tan, Sheldon, Hua, Yingbo, Wang, Hai, and Gupta, Ashish

Subjects
Thermal Modeling, power maps
Abstract

This paper proposes a new thermal modeling method for package design of high-performance microprocessors. The new approach builds the thermal behavioral models from the given accurate temperature and power information by means of the subspace method. The subspace method, however, may suffer predictability problem when the practical power is given as a number of power maps where power inputs are spatially correlated. We show that the input power signal needs to meet some dependency requirements to ensure model predictability. We develop a new algorithm, which generates independent power maps to meet the spatial rank requirement and can also automatically select the order of the resulting thermal models for the given error bounds. Experimental results validates the proposed method on a practical microprocessor package constructed via COMSOL software under practical power signal inputs.

Published
2014

3. System-Level Thermal Modeling and Management for Multi-Core and 3D Microprocessors

Author

Liu, Zao

Subjects
Electrical engineering
Abstract

The continuously scaling down of CMOS technology inevitably increases the power density for high performance microprocessors, which makes thermal effects and related problems urgent and challenging. Unpredicted thermal behavior and on-chip thermal hot spots could lead to performance degradation of microprocessor chips, incurring reliability issues. Hence, it is becoming increasingly important to develop thermal modeling methods to predict the thermal behavior of microprocessor chips, and thermal management techniques to control the on-chip thermal hot spots and thermal related reliability issues.This research focuses on system level thermal behavior modeling and management methods to enable the thermal aware design of high performance microprocessor chips and packages, which also considers the thermal related reliability issues. First, at chip level, a new compact lateral thermal resistance model is proposed to model the lateral thermal behavior of through silicon vias (TSVs), which was largely ignored previously. The proposed lateral thermal model is fully compatible with the existing thermal modeling method of TSVs, and could be integrated into finite difference (FD) simulation to improve the accuracy. Second, targeting at the package level modeling of thermal behavior for microprocessor chip package, the top-down approach building the thermal behavioral models from the given accurate temperature and power information by means of the subspace identification method (SID) is systematically explored in this dissertation research. Power map based approach and piecewise linear modeling method are developed to improve the accuracy of the identified model in presence of thermal nonlinearity and correlated power traces. Third, a more effective architecture level distributed thermal management method is developed to balance the on-chip temperature distribution in this dissertation research. A new temperature metric called effective initial temperature that incorporates both initial temperature and other transient thermal effects is proposed to make optimized task migration decisions in the new distributed thermal management method, leading to more effective reduction of thermal hot spots. The last but not least, since temperature imposes exponential influence on the reliability of the chip, this research also proposes a new system level reliability model derived from fundamental physics principles, in which reliability is modeled as life time resources that are to be consumed as the chip works. Based on this model, a dynamic management method is proposed to effectively balance and compensate the life time resources across all the cores in a multi-core processor system, preventing the chance of early failure of heavily loaded cores.

Published
2014

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