76 results on '"Cristoloveanu, S."'
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2. Undoped junctionless EZ-FET: Model and measurements
3. Superiority of core–shell junctionless FETs
4. Pseudo-MOSFET transient behavior: Experiments, model, substrate and temperature effect
5. A current model for FOI FinFETs with back-gate bias modulation
6. Revisited parasitic bipolar effect in FDSOI MOSFETs: Mechanism, gain extraction and circuit applications
7. A simple test structure for the electrical characterization of front and back channels for advanced SOI technology development
8. Inversion layer electron mobility distribution in fully-depleted silicon-on-insulator MOSFETs
9. Photodiode with low dark current built in silicon-on-insulator using electrostatic doping
10. A2RAM compact modeling: From DC to 1T-DRAM memory operation
11. Impact of contact and channel resistance on the frequency-dependent capacitance and conductance of pseudo-MOSFET
12. New prospects on high on-current and steep subthreshold slope for innovative Tunnel FET architectures
13. Investigation of thin gate-stack Z2-FET devices as capacitor-less memory cells
14. Doping profile extraction in thin SOI films: Application to A2RAM
15. Topology and design investigation on thin film silicon BIMOS device for ESD protection in FD-SOI technology
16. New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube™ integration
17. Kink effect in ultrathin FDSOI MOSFETs
18. A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters
19. Second Harmonic Generation characterization of SOI wafers: Impact of layer thickness and interface electric field
20. Back-gated InGaAs-on-insulator lateral N+NN+ MOSFET: Fabrication and typical conduction mechanisms
21. Low-frequency noise in bare SOI wafers: Experiments and model
22. Fabrication and electrical characterizations of SGOI tunnel FETs with gate length down to 50 nm
23. BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology
24. Second harmonic generation for contactless non-destructive characterization of silicon on insulator wafers
25. High-resolution mobility spectrum analysis of magnetoresistance in fully-depleted silicon-on-insulator MOSFETs
26. Superior performance and Hot Carrier reliability of strained FDSOI nMOSFETs for advanced CMOS technology nodes
27. Parasitic bipolar effect in ultra-thin FD SOI MOSFETs
28. Reliability of ultra-thin buried oxides for multi-VT FDSOI technology
29. Characterization of heavily doped SOI wafers under pseudo-MOSFET configuration
30. A new characterization technique for SOI wafers: Split C(V) in pseudo-MOSFET configuration
31. Tunneling FETs on SOI: Suppression of ambipolar leakage, low-frequency noise behavior, and modeling
32. Detailed investigation of effective field, hole mobility and scattering mechanisms in GeOI and Ge pMOSFETs
33. Low-temperature characterization and modeling of advanced GeOI pMOSFETs: Mobility mechanisms and origin of the parasitic conduction
34. Mobility enhancement by CESL strain in short-channel ultrathin SOI MOSFETs
35. Dynamic body potential variation in FD SOI MOSFETs operated in deep non-equilibrium regime: Model and applications
36. Effects of fin width on memory windows in FinFET ZRAMs
37. Electron magnetoresistance mobility in silicon-on-insulator layers using Kelvin’s technique
38. Dimensional effects and scalability of Meta-Stable Dip (MSD) memory effect for 1T-DRAM SOI MOSFETs
39. Method for 3D electrical parameters dissociation and extraction in multichannel MOSFET (MCFET)
40. Gate-induced floating-body effect (GIFBE) in fully depleted triple-gate n-MOSFETs
41. Silicon on insulator avalanche-impact-ionization transistor with very low switching voltage from ON state to OFF state
42. The Ge condensation technique: A solution for planar SOI/GeOI co-integration for advanced CMOS technologies?
43. NANOSIL network of excellence—silicon-based nanostructures and nanodevices for long-term nanoelectronics applications
44. Experimental evidence of mobility enhancement in short-channel ultra-thin body double-gate MOSFETs by magnetoresistance technique
45. Innovating SOI memory devices based on floating-body effects
46. Monte Carlo simulation of Hall and magnetoresistance mobility in SOI devices
47. High quality Germanium-On-Insulator wafers with excellent hole mobility
48. Transition from partial to full depletion in advanced SOI MOSFETs: Impact of channel length and temperature
49. Thin film fully-depleted SOI four-gate transistors
50. Front- and back-channel mobility in ultrathin SOI-MOSFETs by front-gate split CV method
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