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Edge computing and artificial intelligence (AI), especially deep learning for nowadays, are gradually intersecting to build a novel system, called edge intelligence. However, the development of edge intelligence systems encounters some challenges, and one of these challenges is the \textit{computational gap} between computation-intensive deep learning algorithms and less-capable edge systems. Due to the computational gap, many edge intelligence systems cannot meet the expected performance requirements. To bridge the gap, a plethora of deep learning techniques and optimization methods are proposed in the past years: light-weight deep learning models, network compression, and efficient neural architecture search. Although some reviews or surveys have partially covered this large body of literature, we lack a systematic and comprehensive review to discuss all aspects of these deep learning techniques which are critical for edge intelligence implementation. As various and diverse methods which are applicable to edge systems are proposed intensively, a holistic review would enable edge computing engineers and community to know the state-of-the-art deep learning techniques which are instrumental for edge intelligence and to facilitate the development of edge intelligence systems. This paper surveys the representative and latest deep learning techniques that are useful for edge intelligence systems, including hand-crafted models, model compression, hardware-aware neural architecture search and adaptive deep learning models. Finally, based on observations and simple experiments we conducted, we discuss some future directions. Submitted/Accepted version

Entering the Big Data era leads to the rapid development of web applications which provide high-performance sensitive access on large cloud data centers. HTTPS has been widely deployed as an extension of HTTP by adding an encryption layer of SSL/TLS protocol for secure communication over the Internet. To accelerate the complex crypto computation, specific acceleration instruction set and hardware accelerator are adopted. However, energy consumption has been ignored in the rush for performance. Actually, energy efficiency has become a challenge with the increasing demands for performance and energy saving in data centers. In this paper, we present the EECA, an Energy-Efficient Crypto Acceleration system for HTTPS with OpenSSL. It provides high energy-efficient encryption through HW/SW co-design. The essential idea is to make full use of system resource to exert the superiorities of different crypto acceleration approaches for an energy-efficient design. Experimental results show that, if only do crypto computations with typical encryption algorithm AES-256-CBC, the proposed EECA could get up to 1637.13%, 84.82%, and 966.23% PPW (Performance per Watt) improvement comparing with original software encryption, instruction set acceleration and hardware accelerator, respectively. If considering the whole working flow for end-to-end secure HTTPS based on OpenSSL with cipher suite ECDHE-RSA-AES256-SHA384, EECA could also improve the energy efficiency by up to 422.26%, 40.14% and 96.05% comparing with the original Web server using software, instruction set and hardware accelerators, respectively.

Power substation equipment with multiple configurations use metallic blades to switch to different service configurations. When subjected to earthquakes, a closed blade can produce great coupling effects between two interconnected pieces of the equipment, which substantially affect their dynamic properties and seismic responses. However, knowledge of the coupling effects and their production mechanism is currently insufficient. To investigate coupling effect characteristics, an ultra-high voltage (UHV) disconnect switch with different configurations was tested on a full-scale shaking table. Test results proved that the main blade was a weak connection, which leads inconsistent resonance among different pieces. Furthermore, phase traces of the blade confirm its coupling effects are produced by a nonlinear mechanism. Combined testing results and a numerical calculation were employed to quantitatively estimate the interaction forces raised by the blade. Based on a frequency-domain characteristic analysis, it was found that the nonlinearity was contributed by by the unsteady connection of the blade. Furthermore, this study proved that the blade connection cannot be modeled by a single linear element with any physical parameters.

In dark silicon many-core systems, system-level techniques have been developed to selectively activate nonadjacent cores in physical locations to maintain the allowable power budget and eliminate thermal hotspot. However, this will unexpectedly increase communication overhead due to the longer average distance between active cores in a typical mesh-based Network-on-Chip (NoC), and in turn reduce application performance. Inspired by ARM’s big.LITTLE architecture coupled with Heterogeneous Multi-Processing (HMP) which enables energy-efficient solutions, in this paper, we propose two alternative hardware–software collaborated techniques to address the temperature/communication conflict in the dark silicon era. A Folded Torus-like NoC, FoToNoC, is presented to address the Cluster-switching based heterogeneous system, and a Quad-core-group based NoC, QcNoC, is presented to address the In-kernel switcher based heterogeneous system. Matched management strategies are accordingly proposed to collaboratively solve the trade-offs on inter-core communication, application performance, chip temperature, and system energy-efficiency in different design phases and aspects. Experimental results show that, FoToNoC can improve as large as 36.85 % on application performance, save up to 30.35 % on system energy consumption and reduce chip peak temperature by 4.1 1 ∘ C on average compared with traditional techniques. Furthermore, due to the heterogeneous core organization and the fine-grained optimization on energy-efficiency in QcNoC, averagely 18.40 % reduction on system energy consumption can be achieved with an average 2.2 4 ∘ C reduction on chip peak temperature compared with that in FoToNoC. We further demonstrate the practicality and the effectiveness of the proposed methods by case studies on real-world applications including the industry standard H. 264 decoder and DSP-stone benchmarks.

As an important infrastructure connecting straits or rivers, the construction of fixed links has become an effective measure for improving traffic conditions and promoting socio-economic development in many countries and regions around the world. Thus, it has become a significant topic in the field of transport geography. Taking the Yangtze River Delta as its case area, this study proposes a spatial impact model of trans-Yangtze highway fixed links, consisting of three components: an accessibility model, modified gravity model, and traffic utilisation model, which are used to analyse, respectively, cross-Yangtze accessibility and changes to transport structure, cross-Yangtze urban interaction and changes to economic structure, and the utilisation relationship of fixed links. Making use of existing fixed links while planning and building new ones has become the basis for achieving regional integration and sub-regional cooperation in this area, the aim of which is to create the barrier-free circulation of elements. The results prove that this spatial impact model coincides with reality. The increase in the number of fixed links has significantly shortened cross-river travel time and facilitated a unification of north-south highway networks. It has also promoted the formation of a high-connection urban network along the river. Northern urban nodes have joined the southern economic circle and finally achieved north-south integration. There are complex relationships between fixed links and their hinterlands, showing obvious utilisation gaps between the links. The complete system of trans-Yangtze fixed links is comprised of several river crossing facilities and connected highways. The function of each link is related to its role in the regional highway network. From a small number of fixed links to the realisation of multiple trans-Yangtze bridges and tunnels with easy access to multiple arterial highways, a ‘many-to-many’ spatial pattern is created that ultimately leads to the evolution of regional transport and economic structures.

Currently, exploring effective measures to reduce multiple toxic metals accumulation in rice grains is an urgent issue to be tackled. Pot experiments were thus conducted to explore the effects and mechanisms of foliar spraying with composite sols of silicon (Si) and selenium (Se) during tillering to booting stage on diminishing cadmium (Cd) and lead (Pb) translocation to rice grains and affiliated physiological and biochemical responses in rice seedlings grown in Cd + Pb-polluted soils (positive control). Results showed that Cd and Pb contents in leaves or grains were distinctly below the positive control by the sols. Compared to the positive control, transcriptions of Cd transporter-related genes including OsLCT1, OsCCX2, OsHMA2 and OsPCR1 genes in leaves, and OsLCT1, OsCCX2, TaCNR2 and OSPCR1 in peduncles were downregulated by the increasing sols. Meanwhile, Se-binding protein 1 was evidently upregulated, together to retard Cd and Pb translocation to rice grains. The sols not only upregulated transcriptions of Lhcb1, RbcL, and OsBTF3 genes and production of psbA, Lhcb1 and RbcL proteins, but also increased the chlorophylls contents and RuBP carboxylase activities in the leaves, improving photosynthesis. The sols restrained ROS production from NADPH oxidases, but activated glutathione peroxidase, alleviating oxidative stress and damage. Additionally, Se was significantly enriched and was existed as selenomethionine in the rice grains. However, Pb transporter-related genes remain to be specified. Thus, the composite sols have potential to reduce Cd and Pb accumulation, mitigate oxidative damage, and promote photosynthesis and organic Se enrichment in rice plants under Cd and Pb combined pollution.

In this study, we provide a systematic picture of young Chinese overseas scholars by investigating the "Thousand Youth Talents Program", a flagship talent program in China's current talent-funding system. Through investigating the demographics and the return status of overseas Chinese scholars, we attempt to answer a key question: how do they perform after their return. We conducted an analysis from five aspects, including personal characteristics, return institution statistics, educational background, discipline statistics, and position statistics. We find that most scientists were granted at the age of 33. The proportion of male far exceeds female. The Chinese Academy of Science is the most frequent recipient of returnee talents. The majority returned scientists obtained their doctoral degree from universities ranked 51 to 200 worldwide. The majority of the scholars have majors in life sciences, engineering, and material science. Only 13.65% of total returnees achieved tenure or tenure-track positions while abroad. Combined with publication data from the Scopus database, we are less certain with the effect of return on the post-return performance of young overseas Chinese scientists.

Optical network-on-chip (ONoC) architecture is an emerging communication paradigm that upgrades the traditional electronic NoCs with low latency, ultra-high bandwidth, and good scalability. Processor cores on ONoCs often suffer from overheating problems and it is vital to precisely monitor the temperature of every individual core to perform task scheduling, for ensuring system reliability. In this paper, we propose an on-chip temperature sensing technique. It is implemented by utilizing the existing data communications on ONoCs and the thermo-optic effect of nanophotonic devices. Based on the free communication resources on ONoCs, we propose a polynomial-time algorithm to build auxiliary paths. Combined with the existing data communication paths, we can successfully obtain the on-chip temperature distribution without requiring additional hardware support. Simulation results based on a large number of randomly-generated data communications show that our algorithm is applicable and highly efficient over 94% of cases.

The standby-sparing (SS) is a promising technique which deploys the dual-processor platform, i.e., one primary processor and one spare processor, to achieve fault tolerance for real-time systems. In the existing SS framework, all applications have their backup copies on the spare processor, but, in practice, not all applications on a system are equally important to the system. Some low critical tasks may be traded off for other system objectives. Motivated by this, in this paper, we integrate the concept of criticality into the SS framework. Such integration enables the SS framework to further reduce energy consumption. We propose an offline approach to determine an energy-efficient frequency for the primary processor. Additionally, as the cluster systems are emerging as the mainstream computing platform, we consider the SS technique on the cluster/island systems and propose an algorithm to determine the energy-efficient algorithm for such systems. We evaluate the proposed approach on synthetic tasks and real-platforms. The experimental results demonstrate the effectiveness of our proposed framework in terms of energy efficiency.

Partial Runtime Reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. We make two contributions in this paper. First, we present an efficient algorithm for finding the complete set of Maximal Empty Rectangles on a 2D PRTR FPGA. We also present a HW implementation of the algorithm with negligible runtime overhead. Second, we present an efficient online deadline-constrained task placement algorithm for minimizing area fragmentation on the FPGA by using an area fragmentation metric that takes into account probability distribution of sizes of future task arrivals as well as the time axis. The techniques presented in this paper are useful in an operating system for runtime reconfigurable FPGAs to manage the HW resources on the FPGA when HW tasks that arrive and finish dynamically at runtime.