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With the increasing complexity of graph structures, the current real-world large-scale graphs are being represented by a considerable amount of vertex and edge data. Furthermore, the analysis of a large number of computing nodes has become a very complicated job that requires a large amount of hardware resources. Moreover, in large-scale graph processing, the vertex and edge data show random and sequential memory access patterns at the same time, and this is a major bottleneck in graph processing. In this paper, we present a high-capacity main memory system with an intelligent pattern-aware prefetching engine to overcome the scalability problem and the memory inefficiency of single-machine graph processing. The proposed intelligent pattern-aware prefetching engine is designed to predict and handle sequential or regular patterns and random-access patterns simultaneously. Experimental results demonstrated that the proposed model exhibited performance improvements of 60% over conventional DRAM models, approximately 40% over the existing prefetch models, and about 12.5% over the latest prefetch models.

This research proposes a memory-disk integrated system (MDIS) with pattern analysis based data management method. The proposed system consists of a pattern adaptive prefetcher with DRAM-based dual buffers and a PCM-based persistent memory structure. The PCM-based persistent memory module is exploited as conventional main memory and storage layers simultaneously. In this system, to compensate the PCMs unfavorable characteristics, a pattern analysis based prefetching method by using dual DRAM buffers with a small amount of space are designed as a sort of caching layer. The proposed pattern analysis based data management method monitors the miss rate to determine the prefetch policy, e.g., when and what to prefetch. These schemes enable flexible adaptation to the application execution characteristics showing unpredictable and inconsistent workload patterns. In order to evaluate our system, we implemented a trace-driven simulator system and launched the YCSB on Redis, Apache Storm, Apache Spark, and OpenStack Swift. The experimental result shows that the MDIS with a pattern adaptive prefetcher can reduce the total access time by 13.9% compared to the conventional scheme and thus the overall performance of the memory-disk integrated system improves.

In this study, we designed a KM-Cluster-based pattern adaptive prefetching mechanism for the last-level cache structure to support real time big data management. The goal is to predict future memory access patterns aggressively and accurately through a new self-learning prefetching engine model. The pattern adaptive last-level cache consisted of three major parts: the last-level cache, the first-level prefetching buffer (FLPB) and the second-level prefetching buffer (SLPB). The SLPB efficiently manages the history records of cache blocks evicted from the last-level cache through a self-learning mechanism. A K-means clustering algorithm is used as an SLPB prefetching scheme. Hybrid main memory is constructed using a small portion of the DRAM buffer space and primarily NAND-Flash memory space. The overall performance of our proposed model is evaluated for OpenStack Swift and in-memory database application-Redis. Experimental results show that the proposed architecture reduces the total execution time by 20.96% and power consumption by 31.9% compared to the same last-level cache size with no SLPB structure.