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Wear out in the maximum power point condition of tandem microcrystalline Si/amorphous Si thin film PV modules due to extended light soaking is a well-known effect due to the Staebler–Wronski mechanism [ 1 ]. However, several studies [ [2] , [3] , [4] , [5] , [6] , [7] , [8] ] on a-Si:H single junction and tandem solar cells, have shown that, under suitable conditions of electric field in reverse bias, illumination, especially at well-defined wavelengths (700–800 nm), and temperature conditions, an improvement of the cell main electric parameters is possible. In this work, we report on new stress tests performed on tandem amorphous Silicon PV devices (both non-stabilized and stabilized), highlighting the improvement of their electrical performances, founded both in the tests performed on non-stabilized samples (essentially due to the reverse bias stresses carried out in these tests) and in the outdoor tests on stabilized samples (not subjected to reverse bias stresses) going from morning to afternoon illumination. In the latter tests, the efficiency improvement observed in the afternoon is stable overnight and observed also in the early stages of the morning outdoor test in the following day. Possible causes of such effect are discussed.

Photoelectrochemical water splitting is a promising method to produce H 2 by making use of solar energy. In this paper we report on a photocathode made by p-type crystalline Si covered with an n-type 3C-SiC polycrystalline film, acting as protective layer and transparent emitter. The photoelectrodes exhibit a saturated photocurrent above 30 mA cm −2 . No decay is observed after 9 h under constant current stress at 1 kW m −2 with AM1.5G spectrum illumination. Improvement of the photocurrent value is achieved by covering the 3C-SiC emitter with Au or Pt nanoparticles. Under suitable metal nanoparticles deposition conditions, compared to the samples without nanoparticles, two major effects are observed: first the onset potential is considerably reduced, and second, higher saturated photocurrent is found, up to 38 mA cm −2 , i.e. with a 27% increase. Optical and micro-structural studies on the nanoparticles provide insights on the origin of the observed effects.

Platinum nanostructures are of large interest because of their electrocatalytic properties, enhanced by the high surface/volume ratio, and find applications in numerous fields from fuel cells and electrolyzers, to gas biosensors and nano-biomedicine. In this work we present a simple procedure, based on spontaneous galvanic displacement, to obtain Pt nanoparticles (PtNPs) directly on Si substrate. The nucleation and growth processes involved in the deposition have been studied by Transmission Electron Microscopy and Rutherford Backscattering Spectrometry. The nucleation is quite complex and includes, first, the generation of primary non-growing clusters, with size smaller than 2 nm. Then, for longer deposition times, larger particles are formed, resulting from dynamic coalescence of primary clusters with/or single ion attachment processes. The growth of such larger particles follows the prediction of the classical diffusion limited model. Moreover, the large nanoparticles are poly-crystalline and exhibit a nano-porous structure, in agreement with a mixed aggregative-diffusion limited growth. The nano-porous structure implies a high internal surface area, therefore making these particles particularly promising as efficient catalysts.

In this work, the breakdown transients of metal-oxide-semiconductors (MOS) stacks with InGaAs channels and different oxide layers (Al2O3,HfO2 and Si3N4) have been studied in terms of the time-to-breakdown and the duration of the progressive breakdown regime. It is observed that dielectric layers with higher thermal conductivity show larger transient time during the progressive breakdown regime, and this provides a significant lifetime extension across the entire failure distribution. This is attributed to a lower temperature of the percolation path which reduces local electro-migration. Moreover, the overall results show that the progressive breakdown regime is uncorrelated with the initial degradation rate, and that the bending of failure distribution at low percentiles is exclusively attributed to the progressive increase of the gate current during the breakdown event. Fil: Palumbo, Félix Roberto Mario. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina. Universidad Tecnológica Nacional; Argentina. Comisión Nacional de Energía Atómica. Gerencia del Área Investigaciones y Aplicaciones no Nucleares; Argentina Fil: Lombardo,Salvatore. Consiglio Nazionale delle Ricerche; Italia Fil: Eizenberg, Moshe. Technion - Israel Institute of Technology; Israel

We study resistive switching memories with Hf or Ti metal oxygen exchange layers.STEM dark field and EELS are used to observe the conductive filament.The filament is a cone-shaped metal-rich region in the HfO2 dielectric layer.Composition of the metallic filament is dominated by Hf or Ti depending on the OEL. A detailed physical analysis of the conductive filament electrically formed in HfO2-based resistive switching memory devices with both Hf and Ti metal oxygen exchange layers is presented. The filament, observed by applying transmission electron microscopy (TEM), scanning TEM (STEM), and electron energy loss spectroscopy (EELS) techniques to 50i?50nm2 cells, is a cone-shaped metal-rich region in the HfO2 dielectric of the resistive switching device.

Multiple gate tridimensional memory cells can have several additional advantages besides increased read current and excellent Ion/Ioff ratio, which are inherent in the multiple-gate transistor architecture. We show that tridimensional memory cells with rounded top geometry and SONOS storage stack strongly improve the Fowler–Nordheim tunneling program–erase performances because of an enhanced electric field effect and an increase of the cell coupling factor. Moreover, a remarkable enhancement of the tridimensional cell performances is expected if the blocking silicon oxide and the poly-silicon gate in the SONOS memory stack are replaced with a high-k dielectric and a high work-function metallic control gate.

Dielectric breakdown (BD) of nFETs with TiN metal gates and HfO 2 /interfacial layer with 1.09 nm EOT is studied. Occurrence of progressive BD at low current levels is demonstrated. A new measurement methodology for extraction of the PBD time and its dependence on gate voltage are reported.

In this work we use di-block copolymers self-assembling to make templates for the fabrication of well ordered nano-patterned materials. By using Poly (styrene-b-methylmethacrylate) we obtain a close-packed hexagonal configuration of circular pores, with a tuneable length scale of 10–100 nm. Optimal conditions for long-range order of the template are obtained by varying the synthesis parameters. The self-assembled template is then transferred into different substrates to produce different nano-porous materials. We finally discuss the application of this technique to phase change random access memories, showing that, using di-block copolymer templates as etching mask, nano-patterned SiO2 can be used to form ultra dense amorphous bits arrays in crystalline Ge2Sb2Te5 (GST) films.

In this paper, silicon nanocrystals (Si-NCs) fabricated by Chemical Vapor Deposition (CVD) are successfully integrated in a 32 Mb ATMEL NOR Flash memory product, processed in a 130 nm technology platform. Different Si-NC deposition conditions are explored and the threshold voltage distributions of the arrays are correlated to the Si-NC size/dispersion. Main reliability characteristics, as endurance and data-retention after cycling, are studied. Results obtained on large arrays are related to single cell characteristics. The large set of data measured on arrays clearly demonstrates the robustness of our process and integration scheme.

In this paper, we evaluate the potentialities of hafnium-aluminates (HfAlO) materials as possible candidates for the interpoly dielectrics of future Flash memory devices. HfAlO layers of different thicknesses and compositions are integrated in single-layers and in Oxide/HfAlO/Oxide (OHO) triple-layer stacks, and analyzed in terms of coupling and insulating capabilities. We demonstrate that increasing the Hf content allows reducing the leakage current at high voltages but it results in a stronger leakage current at low voltages. We also show that once normalized in electric fields, the leakage current characteristics are independent of the high-k thickness. The electron conduction modes in these materials, at different temperatures, are also investigated. The activation energy increases with the Hf concentration in the HfAlO alloy, resulting in a higher leakage current at elevated temperatures. Finally, it is demonstrated that the conduction in triple-layer stacks is limited by a Poole–Frenkel conduction in the high-k layers, while the trap contribution in the case of single-layers becomes dominant when the HfAlO layer is thicker than 8 nm.

In this paper, we present the results regarding the electrical and optical characterization of bidimensional arrays of silicon single photon avalanche photodiodes (SPAD). Low average dark count rates and crosstalk probability, good timing jitter and high quantum detection efficiency in the visible range have been measured over 5 × 5 SPAD arrays with 40 μm single pixel active area diameter. Moreover, a very good uniformity of these parameters has been found over the single pixels. These good electro-optical performances make our photodiodes attractive for the fabrication of arrays with a larger number of SPAD. In view of the design of a dense array to be used as a silicon photomultiplier (SiPM) for medical diagnostic tools, 5 × 5 SPAD arrays have been also tested in the photon-resolving mode. Charge spectra show that the arrays, in this configuration, allow to resolve several photoelectron peaks with a good single photoelectron resolution.

In this paper, the hot carrier degradation of laterally diffused nMOSFETs is investigated in detail by the analysis of the fundamental device parameters and charge pumping measurements. Starting from this experimental characterization a new approach based on charge pumping technique is developed to estimate the spatial distribution of the hot carrier damage. This methodology has been applied on test structures, obtaining good results in the prediction of both the interface states and the trapped charges profiling. The supporting assumptions have been verified by fitting to the electrical data and by means of a two-dimensional device simulation.

Si nanocrystal memory cells have been integrated in Flash-like stand-alone devices of 16 Mb along with high and low voltage CMOS logic circuitry. Process integration drawbacks such as nanocrystal residuals in the circuitry region have been eliminated by optimizing etching processes. The program/erase threshold voltage distributions of the memory sectors are well separated and narrow. The voltage distribution width is related to NC sizes, and bigger NCs induce cell reliability problems. Some reliability issues for endurance are also related to the use of ONO dielectric which acts as charge trapping layer, mainly causing program/erase window shift and threshold voltage distribution broadening during endurance.

In this work we present an original study that shows how to reduce the negative fixed charges of atomic layer deposited Al"2O"3. The influence of the aluminium oxide growth temperature on this charge is studied here for the first time. The effect of annealing is also considered, and an optimal process is proposed. Relationship with H content is investigated as well. Finally, influences of these charges on the Al"2O"3 transport properties are analyzed.

The I–V characteristics of ultra-thin gate oxides under progressive breakdown (BD) show a common behavior, indicative of well-defined general physical features of the BD spot. Transmission electron microscopy (TEM) observations give some hints about this structure and on this basis we propose a physical model of the post-BD current, which is in good agreement with data.

Nanoscale structures have been recently proposed as charge storage nodes due to their potential applications for future nanoscale memory devices. Our approach is based on the idea of using Si nanodots as discrete floating gates. To experimentally investigate such potential, we have fabricated MOS structures with Si nanocrystals. The dots have been deposited onto an ultra-thin tunnel oxide by chemical vapor deposition (CVD) of SiH 4 , and then annealed at 1000 °C for 40 s, to crystallize all the dots. After deposition, the dots have been covered by a CVD SiO 2 layer, thus resulting completely embedded into stoichiometric silicon oxide. The nanocrystal density and size have been studied by energy filtered TEM (EFTEM) analysis. An electrostatic force microscope has been used to locally inject and image charge. By applying a relatively large tip voltage and reducing the tip to sample separation down to the contact with the surface sample, a few dots have been charged, by appearing as protrusions on the surface. The charged dots have been monitored for up to 30 min, by showing no discharge effects either vertically, through the double barrier of oxide layers, or laterally, via cross talk effect between other close dots.

In this work we quantify the impact of dots size and dots number fluctuations on the programming window dispersion of multi-nanocrystal memory devices. Concerning dots size distribution, experimental imaging (i.e. transmission electron microscopy) is used and generalized assumptions are made, according to well known theoretical distributions. Concerning dots number distribution, a Poisson dispersion is assumed. Both a Monte Carlo simulation and a deep theoretical analysis (i.e. compound distributions theory) are exploited to assess in two different ways the overall results. Eventually clear guidelines, concerning dot density and dot distribution requirements, are provided for future memory generations.

Silicon quantum dots have been deposited on top of a 3-nm tunnel oxide by Low Pressure Chemical Vapour Deposition (LPCVD) and coated with a 7-nm Chemical Vapour Deposited (CVD) oxide. This stack was then incorporated in Metal-Oxide-Semiconductor structure and used as floating gate of a memory cell. The presence of 3 nm of tunnel oxides allows the injection of the charge by direct tunnel (DT) using low voltages for both program and erase operations. The charge stored in the quantum dots is able to produce a well-detectable flat band shift in the capacitors or, equivalently, a threshold voltage shift in the transistors. Furthermore, due to the presence of SiO 2 between the grains, the lateral charge loss is reduced and, thus, long retention time are possible. In this work we present good memory action characterised by low write voltages, write times of the order of milliseconds and long retention time in spite of the low tunnel oxide thickness. © 2002 Elsevier Science B.V. All rights reserved.

The formation of Si quantum dots on SiO 2 by chemical vapour deposition of SiH 4 is investigated by energy filtered transmission electron microscopy. It is demonstrated that this technique allows to measure size distributions down to dimensions of about 1 nm. This capability allows to put in evidence some important microscopic features of the nucleation process, whose consideration is fundamental to control the Si dot size. These aspects are shown and discussed.

We have investigated the electrical transport and luminescence of Si dots embedded in SiO 2 . The dots have been obtained by high temperature annealing of silicon rich oxides prepared by chemical vapor deposition. Transmission electron microscopy analysis demonstrates the presence of crystalline Si dots with grain radii down to 1 nm. The data of luminescence and electrical transport appear correlated with the dot size distribution. Moreover, the analysis of the electrical characteristics of metal-oxide–semiconductor capacitors with silicon rich oxide films indicates that such systems may reversibly store charge, thus exhibiting the function of a memory.

Time–resolved electrical measurements show transient phenomena occurring during degradation and intrinsic dielectric breakdown of gate oxide layers under constant voltage Fowler–Nordheim stress. We have studied such transients in metal/oxide/semiconductor (MOS) capacitors with an n+ poly-crystalline Si/SiO2/n-type Si stack and with oxide thickness between 35 and 5.6 nm. The data adds new information concerning the intrinsic breakdown mechanism and these are shown and discussed together with the adopted measurement techniques.

We compare polysilicon emitter bipolar transistors fabricated by using diAerent treatments of the interface between single crystal and polycrystalline Si (polysilicon) in the emitter region. One of the treatments consisted in an in situ cleaning of the silicon surface performed in the deposition chamber prior to the polysilicon deposition, resulting in an oxide free interface. A detailed structural and electrical characterization of transistors with and without an oxide free interface is presented. It is shown that, even if common emitter current gain decrease is observed, a strong improvement of base resistance and breakdown voltage can be achieved, while maintaining noticeable high frequency characteristics. # 1999 Elsevier Science Ltd. All rights reserved.

Si/GexSi1−x heterojunction n-p-n bipolar transistors (HBT) with a double polycrystalline silicon (polysilicon) self-aligned structure were fabricated by using high dose Ge implantation for the formation of the Si/GexSi1−x heterostructure and As and BF2 implantation for emitter and base doping. Improvements in electrical characteristics compared to reference Si transistors are demonstrated and related to a band gap narrowing in the base region and to a reduction of B diffusion.

We have investigated the relationship between microstructure and electrical conductivity in semi-insulating polycrystalline silicon (SIPOS) with oxygen concentrations in the 2–35 at.% range and the effect of doping with boron, phosphorus, arsenic and erbium by ion implantation. SIPOS thin films are mixtures of silicon and silicon oxide phases. The chemical and morphological evolution of these phases upon annealing is emphasized. Electrical conductivity measurements are interpreted in terms of a physical model containing few free parameters related to the material microstructure. A direct extension of this model explains also the conductivity increase in SIPOS doped with elements of the third or the fifth group. In the last part of the paper, data of electroluminescence at 1.54 μm in Er-implanted SIPOS due to intra-4f transitions of the Er3+ ion are shown and discussed.

Epitaxial Si Ge x Si 1 − x heterojunctions were formed by high dose Ge ion implantation in Si followed by rapid thermal annealing at 1000°C for 10 s. This technique was adopted to fabricate Si Ge x Si 1 − x heterojunction n-p-n bipolar transistors (HBT) using a self-aligned, double polycrystalline silicon process commonly used for fast Si bipolar transistors. The devices are characterized by a 60 nm wide neutral base with a Ge concentration peak of ≈ 7 at.% at the base-collector junction. Good static and dynamic electrical characteristics are demonstrated and discussed.

Epitaxial Si/GexSi1-x heterojunctions were formed by high dose Ge ion implantation in Si followed by solid phase epitaxy. This technique was adopted for fabricating Si/GexSi1-x heterojunction n-p-n bipolar transistors (HBT). We used a standard self-aligned, double polycrystalline silicon process for Si with the addition of the high dose Ge implantation. The transistors are characterized by a 60 nm wide neutral base with a Ge concentration peak of ≈ 8 at.% at the base-collector junction. The devices show very good static electrical characteristics, and compared with Si homojunction transistors with similar values of current gain and Early voltage, show base resistances more than two times lower. In addition to the HBTs, also the feasibility of GexSi1-x metal-oxide-semiconductor field-effect transistors (MOSFET) by ion implantation has been explored by investigating the GexSi1-x oxidation process.

We demonstrate sharp room-temperature electroluminescence at 1.54 μm due to intra-4f transitions of Er3+ in semi-insulating polycrystalline silicon (SIPOS) implanted with Er and annealed for implant damage recovery. Our measurements refer to SIPOS containing ≈ 30 at.% O, doped with Er to concentrations of about 1 at.% and annealed at a temperature in the 400–1100°C range. The luminescence has been excited either by optically pumping with an Ar laser or by biasing suitable metal-SIPOS-p+ silicon devices.

In this paper we show that single-photon avalanche detectors (SPADs) may have a strong potential as very sensitive on-wafer tools for lifetime monitoring, given their simple fabrication process and their straightforward use in the measurements. We have fabricated Si SPADs with n + -p structures and we show that dark counting has a simple exponential dependence on time, thus making it possible to extract a single lifetime parameter.

We report experimental investigations on the amorphous-to-crystal transition in silicon during ion bombardment. The transition was induced by 600 keV Kr irradiation of an amorphous layer in contact with a crystalline substrate. The growth rate depends on the substrate temperature, orientation and the logarithm of the dopant concentration. The crystallization was also stimulated in absence of a planar seed by irradiating an amorphous silicon layer deposited on a thick layer of SiO2. The presence of crystal seeds with radius of the order of a few nanometers in the as-deposited material has been observed. The growth of these seeds is controlled by the motion of [111] boundaries. The grain density is constant with the irradiation dose but it decreases with the substrate temperature. All of the data are discussed in terms of a phenomenological model based on the assumption that the same defects are responsible for the amorphous-to-crystal transition both in pure thermal and in ion-assisted processes.

Erratum to ‘‘Integration of CVD silicon nanocrystals in a 32 Mb NOR flash memory” [Solid State Electronics 52(9) (2008) 1452–1459] S. Jacob *, B. De Salvo , L. Perniola , G. Festes , S. Bodnar , R. Coppard , J.F. Thiery , T. Pate-Cazal , C. Bongiorno , S. Lombardo , J. Dufourcq , E. Jalaguier , T. Pedron , F. Boulanger , S. Deleonibus b a Technology Development ATMEL Rousset, Avenue Olivier Perroy, 13790 Rousset, France CEA, LITEN/DTNM/LCH, 17 rue des martyrs, 38054 Grenoble Cedex 9, France CNR-IMM, Catania, Italy