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Today's data communication systems are demanding increasing off-chip data rates. To satisfy this demand, high-speed serial links are used, saving area and power dissipation compared to highly parallel buses. However, power dissipation and noise generated by this system is still a critical issue. In this article, a novel approach using differential current mode is presented, which combines low power dissipation with low noise generated due to the reduced power transmission.

Mathematical morphology (MM) appears as a theory that can solve some drawbacks of the classical lineal image processing. Linear filters generate a spatial distortion from initial image, what gives as result that specific algorithms are usually needed for each process with a complexity that cannot be implemented in VLSI systems for real time image processing. MM overcome the inherent drawbacks of the linear processing based on the comparison of an initial image with some well-known geometric figures. In this paper we present the implementation of a specific processor that computes MM basic operations. Using a clock frequency of 250 MHz this processor is able to handle real time 512×512 pixels video images. MM allows non-linear processing of images and it is based on dilation and erosion operations using a geometric figure called structural element (SE). More complex image processing can be performed using these two basic operations. In this implementation the SE of 3×3 pixels was chosen. 0.6 μm HGaAs standard cells technology, from Vitesse Semiconductor Corporation, has been used achieving a logic level gate description with the possibility of migration to another technologies.