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This paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range from room temperature up to 500 K. The model validation is performed by comparison against tridimensional numerical simulation and experimental data showing very good agreement, with continuous description of drain current and its derivatives in all regions of operation and temperatures.

This paper deals with the behavior of degradation by NBTI effect in pMOS junctionless nanowire transistors (JNTs). The analysis has been performed through measurements followed by 3D numerical simulations and has shown that the increase in the oxygen precursors density close to the interface leads to the reduction of the saturation in the NBTI effect when the devices operate in partial depletion regime. Such effect can be associated to the change in the flatband voltage to more negative values as well as the threshold voltage with the increase in the precursor density. In the sequence of the work, it was shown that, as the operation temperature rises, there is an increase in the degradation of the threshold voltage due to NBTI, which is more pronounced for larger gate voltages. It was concluded that this effect could be associated to the increase in the recombination rate with the temperature, which enables the occupation of a larger amount of traps.

The ballistic hole transport properties in rectangular cross-sectional germanium nanowire transistors with various geometries were studied based on the “Top of the Barrier” model. Then, by an extension of this model, the quasi-ballistic hole transport was discussed taking into account phonon and surface roughness scattering in the channel and source-to-drain direct tunneling. Among several nanowire geometries targeted in this study, the [1 1 0]-oriented nanowire with large height along [1 1 ¯ 0] ([1 1 0]/(1 1 ¯ 0) NW) exhibited the largest ballistic current. This was understood from its large density of states and resulting high hole density. Large density of states, however, enhances backscattering in the channel. An approximation analysis of quasi-ballistic transport suggested that the [1 1 0]/(0 0 1) NW with higher mobility can outperform [1 1 0]/(1 1 ¯ 0) NW when scattering and tunneling are considered.

We investigated the BSIM4 parameter extraction procedure for tri-gate Si nanowire transistors with different geometries and fabrication processes. SPICE modeling tool was used to extract the parameter from Id-Vg to Id-Vd characteristics with liner and saturation region. Dependence of source/drain parasitic resistances on nanowire width and gate sidewall thickness can be observed on the extracted parameters. Furthermore, parasitic capacitance was extracted from three-dimensional TCAD simulation with our fabricated device structure. Single sets of parameters can reproduce I-V characteristics with Lg down to 35nm for n-channel nanowire transistors. It was found that the extracted parameters will be a useful tool for characterizing the circuit performance of nanowire transistor. Therefore, this procedure is applicable to extract the BSIM4 model parameters for NW Tr. as well as other multi-gate FETs. SPICE parameters of BSIM4 were successfully extracted for tri-gate NW Tr.Dependence of Rsd on Tr. geometry and process can be observed on the parameter.Single sets of parameters for Lg down to 35nm were obtained.The parameters will be a useful tool for characterizing the circuit performance.

In this paper, we present the fabrication and characterization of gate-all-around (GAA) junctionless (JL) poly-Si nanowire (NW) transistors with a dual-gated configuration, in which a sub-gate is placed over a shorter main-gate in order to control the NW potential for the offset regions between the main-gate and S/D regions. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. Inevitable misalignment of lithographic patterning for the main-gate structure leads to asymmetrical channel offsets between the main-gate to source pad and to drain pad, respectively. That is, the length of un-gated NW close to the source pad differs from that to the drain pad. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end. Such a trend become less profound as the sub-gate bias increases.

We present experimental results for junctionless nanowire transistors (JNTs) with different gate alignments to the nanowire. Devices with nanowire source/drain extensions (NSDE) show high series source/drain resistance due to the low doped nanowire extensions, which causes lower drive current and larger device performance variations comparing with devices in which the gate electrode overlaps with the source/drain contact pads (GSD). Due to the improved on-current GSD devices exhibit much higher cutoff frequency. The high fringing field in the NSDE JNT results in degradation of SS. An optimized “dumbbell” shape JNT structure is proposed to further improve the device performance. Our preliminary simulations demonstrate higher on-currents but also larger parasitic capacitances for the dumbbell JNT. However, the RF performance of the dumbbell JNT is still improved with a factor similar to our experiments. Much smaller fringing field for the dumbbell JNT is expected from the simulation, which can cause less device variations.

The increase of hot carrier degradation with decreasing wire width in nanowire gate-all-around (GAA) MOSFETs has been investigated through experiment and device simulation. From the systematical analysis of measurement and simulation, it is found that the increase of device degradation in narrow devices is dominantly governed by the increased current density, the large lateral and vertical fields, and the increased interface state generation rather than by the reduced floating body effects. The more significant hot carrier degradation with decreasing wire width is likely to be proportional to the surface-to-volume ratio of nanowires.

In this work we propose an analytical model for the threshold voltage ( V T ) of III–V cylindrical nanowires, that takes into consideration the two dimensional quantum confinement of the carriers, the Fermi–Dirac statistics, the wave-function penetration into the gate insulator and the non-parabolicity of the conduction band structure. A simple expression for V T is obtained assuming some suitable approximations. The model results are compared to those of a 2D self consistent Schrodinger–Poisson solver, demonstrating a good fit for different III–V materials, insulator thicknesses and nanowire sizes with diameter down to 5 nm. The V T dependence on the confinement effective mass is discussed. The different contributions to V T are analyzed showing significant variations among different III–V materials.

The aim of this work is to propose a semi-analytical model for the low frequency noise caused by interface traps in Triple-Gate Junctionless Nanowire Transistors. The proposed model is based on a drain current model, which includes short channel effects influence. The surface potential and the occupied trap density equations are solved self consistently to obtain the traps influence in the static drain current, which is used to determine the trap-related noise. In this work, the low frequency noise of traps in discrete levels is analyzed. The model has been validated with 3D simulations considering different devices characteristics, biases and trap levels. Experimental results have also been used to demonstrate the model suitability.

Device design for cylindrical Si nanowire field-effect-transistors is studied in short channel regime of 22 nm technology generations and beyond. A two-dimensional quasi-analytical model reveals that a critical minimum channel length is 1.5 times as long as a Si nanowire diameter to suppress the short channel effects. The quantum mechanical effect due to the structural carrier confinement in nanowire with narrow diameter deteriorates both the threshold voltage roll-offs and the subthreshold characteristics.

The paper presents a basis expansion scheme for atomistic transport simulations in nanowire MOSFETs. Two simple methods are formulated to calculate current carrying states using a low-dimensional device Hamiltonian in the scattering basis representation. The proposed methods are computationally very cheap and their utility is confirmed by test self-consistent calculations in a p-Si nanowire device.

We have fabricated n-channel junctionless nanowire transistors with gate lengths in the range of 20–250 nm, and have compared their electrical performances with conventional inversion-mode nanowire transistors. The junctionless tri-gate transistor with a gate length of 20 nm showed excellent electrical characteristics with a high Ion/Ioff ratio (>106), good subthreshold slope (∼79 mV/dec), and low drain-induced barrier lowering (∼10 mV/V). The simpler fabrication process without junction formation results in improved short-channel characteristics compared to the inversion-mode devices, and also makes the junctionless nanowire transistor a promising candidate for sub 22-nm technology nodes.

Organic nanowires self-assembled from small-molecule semiconductors and conducting polymers have attracted an enormous amount of interest for use in organic field-effect transistors. This new class of materials offers solution processability, the potential for elucidating transport mechanisms and structure-property relationships, and the realization of high-performance transistors that rival the performance of amorphous Si. We discuss the self-assembly of one-dimensional, single-crystalline organic nanowires, show the structures of commonly employed organic semiconductors, and review some of the advances in this field.