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Alzheimer's disease is a chronic neurodegenerative disease. Preparation of transdermal patches is a useful strategy for management of the disease. The transdermal patches bearing Rivastigmine tartarate were prepared using solvent casting method to provide good drug content uniformity. Transdermal patches were characterized for various attributions viz. patch weight, patch thickness, folding endurance, surface morphology study, X-Ray diffraction study, Differential Scanning Calorimetry, tensile strength, surface pH, percent swelling, percent moisture sorption, drug content uniformity, In vitro release study, and ex-vivo study. Results of in vitro drug release studies clearly indicate that the drug release governed polymer interaction. No lag time was observed then reduction in drug release rate was observed. Extended drug release of 75.15 ± 1.43% within 24 h was observed with formulation. The results of the permeation study indicated that the rate of drug permeation was slow and it was found that 61 ± 1.43% of Rivastigmine tartrate could permeate through the skin membrane in 24 h. In the light of the above mentioned considerations, it is clear that the developed transdermal patch bearing Rivastigmine tartrate was retained in skin layer and delivers the therapeutic amount of drug in blood for longer time. This indicates the potential use of transdermal patches in the treatment of Alzheimer disease.

The need of Mechanical Taillift is due to inconvenience caused during loading and unloading of goods. It helps in reducing the chance of injuries, saves time & increases the load lifting capacity. It is mounted on trucks for loading & unloading purposes. Tail lift make it much easier to safely load & unload and are synonymous with cost efficiency, flexibility & a high level of operating comfort for user. It can be mounted or unmounted from truck according to user requirement. It takes power from truck battery to operate and can be operated by single user only. More general legal requirements of the safety, health and welfare at work act 2005 and the safety, health and welfare at work (general application) regulations 2007 includes all risk associated with the use of taillift must be written down in the safety statement. People who are to operate the taillift must be trained in its safe use. We have designed the CAD 3 model in Solidworks while it has been analyzed on Ansys workbench 18.0

Vulnerability discovery models allow prediction of the number of vulnerabilities that are likely to be discovered in the future. Hence, they allow the vendors and the end users to manage risk by optimizing resource allocation. Most vulnerability discovery models proposed use the time as an independent variable. Effort-based modeling has also been proposed, which requires the use of market share data. Here, the feasibility of characterizing the vulnerability discovery process in the two major HTTP servers, Apache and IIS, is quantitatively examined using both time and effort-based vulnerability discovery models, using data spanning more than a decade. The data used incorporates the effect of software evolution for both servers. In addition to aggregate vulnerabilities, different groups of vulnerabilities classified using both the error types and severity levels are also examined. Results show that the selected vulnerability discovery models of both types can fit the data of the two HTTP servers very well. Results also suggest that separate modeling for an individual class of vulnerabilities can be done. In addition to the model fitting, predictive capabilities of the two models are also examined. The results demonstrate the applicability of quantitative methods to widely-used products, which have undergone evolution.

In this work we examine the feasibility of quantitatively characterizing some aspects of security. In particular, we investigate if it is possible to predict the number of vulnerabilities that can potentially be present in a software system but may not have been found yet. We use several major operating systems as representatives of complex software systems. The data on vulnerabilities discovered in these systems are analyzed. We examine the results to determine if the density of vulnerabilities in a program is a useful measure. We also address the question about what fraction of software defects are security related, i.e., are vulnerabilities. We examine the dynamics of vulnerability discovery hypothesizing that it may lead us to an estimate of the magnitude of the undiscovered vulnerabilities still present in the system. We consider the vulnerability discovery rate to see if models can be developed to project future trends. Finally, we use the data for both commercial and open-source systems to determine whether the key observations are generally applicable. Our results indicate that the values of vulnerability densities fall within a range of values, just like the commonly used measure of defect density for general defects. Our examination also reveals that it is possible to model the vulnerability discovery using a logistic model that can sometimes be approximated by a linear model.

The main considerations for built-in self-test (BIST) for complex circuits are fault coverage, test time, and hardware overhead. In the BIST technique, exhaustive or pseudo-exhaustive testing is used to test the combinational logic in a register sandwich. If register sandwiches can be identified in a complex digitial system, it is possible to test several of them in parallel using the built-in logic block observation (BILBO) technique. Concurrent built-in logic block observation (CBILBO) technique can further improve the test time, but it requires significant hardware overhead. A systematic scheduling technique is suggested to optimize parallel tests of register sandwiches. Techniques are proposed to deal with shared registers for parallel testing. The proposed method attempts to reduce further the test time while only modestly increasing the hardware overhead.

Stuck-on and leakage faults are among the major failure modes for CMOS ICS. The only definite way to test for these faults is to monitor the supply current under different test vectors. To evaluate the effectiveness of this test technique, distribution of normal and abnormal conductance values has to be obtained. This paper presents two procedures which can be used to extract the required information from measurable data. Experimental data for a number of CMOS chips has been analyzed and the results are presented.