Search

Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this “stacked via” approach is Ni/TiN/W. We demonstrate that the second “stacked Via” is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm µm.

Process compatible high- k dielectric thin films are one of the key solutions to develop high performance metal–insulator–metal (MIM) structures for future microelectronic devices. Engineered cerium–aluminate (Ce x Al 2– x O 3 ) thin films were deposited on titanium nitride metal electrodes by electron-beam co-evaporation of ceria and alumina in a molecular beam deposition chamber. X-ray photoelectron spectroscopy clearly reveals that Ce cations can be stabilized in the 3+ valence state in Ce x Al 2– x O 3 up to x = 0.7 by accommodation in the alumina host matrix. Higher Ce content was observed to result in cerium dioxide segregation in cerium aluminate matrix, probably due to the chemical tendency of Ce cations to exist rather in the 4+ than in the 3+ state. Electrical characterization of the X-ray amorphous Ce 0.7 Al 1.3 O 3 films reveals a dielectric constant value of about 11 and leakage current lower than 10 −4 A/cm 2 . No parasitic low- k interface formation between the high- k Ce 0.7 Al 1.3 O 3 film and the TiN metal electrode is detected.