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Mobile robots are playing an important role in modern industries. The deployment of robots which act as mobile helpers in a wireless network is rarely considered in the existing studies of the device-to-device (D2D) caching schemes. In this paper, we investigate the optimal caching scheme for D2D networks with multiple robot helpers with large cache size. An improved caching scheme named robot helper aided caching (RHAC) scheme is proposed to optimize the system performance by moving the robot helpers to the optimal positions. The optimal locations of the robot helpers can be found based on partitioned adaptive particle swarm optimization (PAPSO) algorithm. And based on these two algorithms, we propose a mobility-aware optimization strategy for the robot helpers. The simulation results demonstrate that compared with other conventional caching schemes, the proposed RHAC scheme can bring significant performance improvements in terms of hitting probability, cost, delay and energy consumption. Furthermore, the location distribution and mobility of the robot helpers are studied, which provides a reference for introducing robot helpers into different scenarios such as smart factories.

Proxy cache access speeds and decreases load time. There is an uncertainty regarding cache level 2 which you neglect. This research shall investigate the L1 cache, primary cache, and L2 cache as a secondary proxy server cache. LRU is typically utilised instead of cache. LRU for cold cache removal used to be a time-consuming process, but it isn't particularly efficient today. The performance of the cache L1 used LRU and L2 used LRU_AVL has risen with these solutions. The output is the LRU_AVL among other ways that utilize LRU tables and graphs. proxy cache LRU, LRU_AVL, and LRU_BST have average time of access calculated. Median access time is estimated using Python tools including Pandas, MatPlotLib as well as LRU, LRU_AVL, and LRU_BST. This research will anticipate the average period of usage of LRU, LRU_AVL, and LRU_BST cache algorithms.

Shared memory architectures are pervasive in the multicore technology era. Still, sequential and parallel applications use most of the data as private in a multicore system. Recent proposals using this observation and driven by a classification of private/shared memory data can reduce the coherence directory area or the memory access latency. The effectiveness of these proposals depends on the accuracy of the classification. The existing proposals perform the private/shared classification at page granularity, leading to a miss-classification and reducing the number of detected private memory blocks. We propose a mechanism able to accurately classify memory blocks using the existing translation lookaside buffers (TLB), which increases the effectiveness of proposals relying on a private/shared classification. Our experimental results show that the proposed scheme reduces L1 cache misses by 25% compared to a page-grain classification approach, which translates into an improvement in system performance by 8.0% with respect to a page-grain approach.

In a typical embedded CPU, large on-chip storage is critical to meet high performance requirements. However, the fast increasing size of the on-chip storage based on traditional SRAM cells makes the area cost and energy consumption unsustainable for future embedded applications. Replacing SRAM with DRAM on the CPU’s chip is generally considered not worthwhile because DRAM is not compatible with the common CMOS logic and requires additional processing steps beyond what is required for CMOS. However a special DRAM technology, Gain-Cell embedded-DRAM (GC-eDRAM) [1] , [2] , [3] is logic compatible and retains some of the good properties of DRAM (small and low power). In this paper we evaluate the performance of a novel hybrid cache memory where the data array, generally populated with SRAM cells, is replaced with GC-eDRAM cells while the tag array continues to use SRAM cells. Our evaluation of this cache demonstrates that, compared to the conventional SRAM-based designs, our novel architecture exhibits comparable performance with less energy consumption and smaller silicon area, enabling the sustainable on-chip storage scaling for future embedded CPUs.

The Internet of things (IoT) is a new network concept. Based on the Internet, the idea of connecting everything is proposed, which is likely to become the development direction of computer and communication in the future. Meanwhile, as a disruptive new communication network model, Information-Centric Network (ICN) has become a hot spot in the field of future network architecture research in recent years. ICN is information-centric, and uses the name of the information to implement data identification, retrieval, and routing and forwarding. The information centric network uses the cache as a built-in structure, and nodes store all the data that flows by default, so that subsequent requests can be responded to as soon as possible. In the actual network, the spread and trend of an information constantly change with time, and the popularity of the information is different in different time periods. However, the existing ICN native caching mechanism ignores the correlation between contents, and the existing relevant research makes insufficient use of content relevance. In this paper may exist a certain correlation between nodes have access to the content of the facts, we design a path cache method based on the correlation content, by discovering target content and the correlation between nodes store content, at the same time considering the node position in the path, make caching decisions, make the cache memory more efficient. The feasibility and effectiveness of the proposed method are verified by simulation experiments under different parameters.

A quantitative and yield analysis of single bit cache memory architecture has been analyzed. A single bit cache memory architecture is made up of a write driver circuit, static random access memory cell, and sense amplifiers such as voltage mode sense amplifier and a current-mode sense amplifier. Apart from it, the power reduction technique has been applied over different blocks of single bit cache memory architecture such as sense amplifiers and static random access memory cell, to optimize the power consumption of the circuit. To check the robustness of the circuit monte carlo simulation and process corner simulation also have been done. The conclusion arises that single bit cache memory architecture having volatge mode sense amplifier with forced stack technique over static random access memory in an architecture consumes the lowest power (9.108 µW) with an area of 6.613 × 30.48 mm2.

This paper investigates how various caching strategies can reduce the computational effort of the active set method (ASM) applied to solve constrained model predictive control problems with quadratic objective function and linear constraints. Specifically, we show that during closed-loop operation, the active set method often re-visits the same combination of active constraints while searching for optimal control inputs by factoring Karush-Kuhn-Tucker (KKT) systems. By storing the factors of the corresponding KKT system in a cache, these repetitive calculations can be simplified to a mere cache search and evaluation of the appropriate factors. Since the cache memory is typically fairly restricted, the efficiency of the scheme depends on how well the cache space can be utilized. In particular, when the cache is fully utilized, and a new element needs to be stored, the cache replacement policy needs to determine which element should be removed from the cache to make space for the new one. In the paper, we scrutinize various cache replacement policies and how well they work as a function of the cache size. The results show that by using a cache of modest size, the number of computational operations performed by the ASM can be reduced by up to 80%, thus significantly accelerating the implementation of model predictive control.

Threads running on different cores of chip multiprocessors (CMP) can cause thread performance degradation due to contention for shared resources such as shared L2 cache. Some studies have shown that thread co-scheduling can effectively reduce contention for shared resources. However, in a multi-core system with shared caches, mutual interference between threads is unpredictable. As the number of cores increases, we are unlikely to exhaust all possible co-scheduling schemes. In this paper, a novel fairness-aware thread co-scheduling algorithm base on non-cooperative game is proposed to reduce L2 cache misses. We tried to improve the overall performance of the system by scheduling threads fairly. The originality of this work is to model thread scheduling using a non-cooperative game. The execution time of a thread varies depending on which threads are running on other cores of the same chip, because different thread combinations result in different levels of cache contention. Given the interdependence and competition between threads on the CMP architecture, non-cooperative game is used to solve the problem of thread co-scheduling where each thread is considered as a participant in the game. An iterative algorithm (IA) is proposed to solve the Nash equilibrium of the non-cooperative game in this paper. Subsequently, it is theoretically proved that IA has a potential game process and finally proves that IA can converge to Nash equilibrium in N iterations, where N is the number of threads. The co-scheduling scheme of all threads is obtained by solving the Nash equilibrium of the IA. Finally, the convergence and effectiveness of IA proposed in this paper is verified by experiments. In addition, we use the cache partition to improve the performance of IA. Experimental results show that the number of total cache misses of IA is less than that of the default scheduling algorithm, IA combined with cache partitioning can further reduce the total cache misses.

Over past few decades, various ways have been conducted through side channel attacks to steal information for a computer system. Unlike conventional hardware-based methods, i.e. power-based side channel, side channel on micro-architecture does not require any physical access to the devices under interest. Instead, only compromised programs need to be co-located on the same machine as the victim. For some other scenarios, malicious users can form side channel information leveraging the timing of program execution. In this survey, we are presenting a comprehensive taxonomy of attack vectors in stack cache memory modules, which mostly are the points of attack by side channel. Due to the significance of side channel attacks, the challenges and overheads of these attack vectors are described through the course of this study. We discuss what side channel attacks are, how they are used, and how they can be prevented through the use of obfuscation techniques. To accomplish this, we introduce the findings of a number of relevant works. These include successful attacks on systems using novel variations of side channel attacks and preventative measures against the attacks.

In-network caching is considered to be a vital part of the Internet for future applications (e.g., Internet of Things). One proposal that has attracted interest in recent years, Named Data Networking (NDN), aims to facilitate in-network caching by locating content by name. However, the efficiency of in-network caching has been questioned by experts. Data correlation among caches builds strong dependencies between caches at the edge and in the core. That dependency makes analyzing network performance difficult. This paper proposes CCndnS (Content Caching strategy for NDN with Skip), a caching policy to break the dependencies among caches, thus facilitating the design of an efficient data placement algorithm. Specifically, each cache – regardless of its location in the network – should receive an independent set of requests; otherwise, only misses from downstream caches make their way to the upstream caches, i.e. a filtering effect that induces a correlation among the caches. CCndnS breaks a file into smaller segments and spreads them in the path between requester and publisher in a way that the head of the file (the first segment) should be cached at the edge router close to the requester and the tail far from the requester and towards the content provider. Requests for a segment skip searching caches in its path, to search only the cache with the segment of interest. That reduces the number of futile checks on caches, and thus the delay from memory accesses. This mechanism also decouples the caches, so there is a simple analytical model for cache performance in the network. We illustrate an application of the model to enforce a Service Level Agreement (SLA) between a content provider and the caching system proposed in this paper. The model can be used for cache provisioning for two purposes: (1) To specify the cache size to be reserved for specific contents to reach some desired performance. For instance, if the client of an SLA requires a 50% cache hit for its content at each router, the model can be used to determine the cache size that needs to be reserved to reach the 50% hit rate. (2) To calculate the effect of such reservations on other contents that use the routers covered by the SLA. The design, analysis, and application are tested with extensive simulations.

Single instruction multiple data (SIMD) extensions are one of the most significant capabilities of recent General Purpose Processors (GPPs) which improves the performance of applications with less hardware modification. Each GPP vendor such as HP, Sun, Intel, and AMD has its particular Instruction Set Architecture (ISA) and SIMD micro-architecture with different perspectives. Intel expanded SIMD technologies from hardware and software point of view. It has introduced SIMD technologies such as MultiMedia eXtensions (MMX), Streaming SIMD Extensions (SSE), Advanced Vector eXtensions (AVX), Fused Multiply Add (FMA) and AVX-512 sets. During micro-processors developments path, register width has been extended from 64 bits to 512 bits and number of vector registers has been increased from 8 to 32. Wider registers provide more parallelism ways and more registers reduce extra data movement to the cache memory. In order to gain the advantages of SIMD extensions, many programming approaches have been developed. Compiler Automatic Vectorization (CAV) as an implicit vectorization approach, provides simple and easy SIMDization tools. While, performance improvement of CAV is not always granted, most compilers auto-vectorize simple loops. On the other hand, for explicit vectorization, Intrinsic Programming Model (IPM) provides low-level access to vector registers for SIMDizing. However, programming with IPM requires great amount of expertise especially in low-level architecture feature, thus, choosing the suitable instructions and vectorization methodology for mapping to a certain algorithm is important. Moreover, portability, compatibility, scalability and compiler optimization might limit the advantage of IPM. Our goal in this paper is as follows. First, we provide a review of SIMD technology in general and Intel’s SIMD extensions in particular. Second, some SIMD features of Intel SIMD technologies, MMX, SSEs, AVX, and FMA in terms of ISA, vector width, and SIMD programming tools are comparatively discussed. Third, in order to compare the performance of different auto-vectorizers and IPM approaches using Intel C++ compiler (ICC), GNU Compiler Collection (GCC) and Low Level Virtual Machine (LLVM), we map and implement some representative multimedia kernels on AVX and AVX2 extensions. Finally, our experimental results show that although the performance improvement using IPM approach is higher than CAVs, programmer needs more programming efforts and knows different mapping strategists. Therefore, extending auto-vectorizers abilities to generate more efficient vectorized codes is an important issue in different compilers.

This study focuses on developing the algorithms for solving 3D inverse problems of ultrasound tomography using GPU clusters and general-purpose supercomputers. The computing capabilities of these supercomputer architectures in application to wave tomography are compared via numerical simulations. Parallel gradient-based iterative algorithms designed to solve coefficient inverse problems for the wave equation are proposed. We show that layer-by-layer wave tomography can be efficiently performed using both CPU- and GPU-based supercomputers. Solving 3D coefficient inverse problems is much more computationally expensive. A general-purpose (CPU-based) system capable of reconstructing 3D images should be equipped with either a sufficient number of memory access channels or a large number of computing cores with large cache memory and high-speed communication network. Such a system would be very large and expensive. Therefore, the most promising solution is to develop dedicated GPU-based supercomputers. From the applications perspective, this study focuses on problems of developing ultrasound tomography devices for breast cancer diagnosis. Computer simulations show that a GPU cluster capable of performing 3D image reconstruction within reasonable time fits in a single rack and can be incorporated into medical ultrasound tomography facilities.

The Network-on-Chip(NoC) is a promising alternative to traditional bus-based architectures that has been widely applied to interconnect multi/many-core systems due to its scalable and modular design. Undoubtedly, the memory wall problem is one of the most important challenges; however, this problem can now be somewhat be alleviated by cache subsystems. In this paper, to overcome the high resource consumption and low data-sharing rate problems of the private cache scheme, we propose a partially shared cache structure and a corresponding replacement algorithm based on a mesh NoC. In this scheme, the L2 cache is shared by each group of four cores that connected as a cluster to a given node by the local bus. To maximize the performance of this partially shared cache structure, we propose a core-aware re-reference interval prediction (CA-RRIP) replacement algorithm. The algorithm performs dynamic virtual partitioning on the partially shared cache; the core that initiated the cache access request will be given top priority when a cache area needs to be replaced or inserted. This approach guarantees cache exclusivity and can mitigate interactions among cores using different access patterns. We implement the traditional private, the proposed partially shared and the row-shared cache subsystems in our experiments. The comparisons indicate that the overall system resource occupation can be reduced by 20% with the same number of cores, and the instructions per cycle(IPC) of the system could increase by up to 49.2%. Moreover, the system throughput(STP) increased by an average of 5.89%. Our experimental results showed that the proposed CA-RRIP algorithm also reduces the average cache miss rate of the system under various cache access patterns.

Sentinel-1 (S-1) TOPS data are widely applied in InSAR applications to monitor earthquakes and landslides. The large S-1 coverage however, leads to a high computational cost when executing InSAR techniques. Thus, we develop a GPU accelerated S-1 InSAR processing method implemented on a personal desktop. In the proposed method, computationally expensive modules including geometric coregistration, resampling, Enhanced Spectral Diversity, and coherence estimation, are implemented using CUDA. In addition, several optimizations are employed to enhance the efficiency of these modules. We select an efficient approximation method in the geometric coregistration module, and improve the GPU memory access efficiency in the resampling module through the GPU texture memory, temporary register array, and a configuration with more L1 cache. We develop a novel GPU-based parallel coherence estimation algorithm in ESD and coherence estimation modules, and use the asynchronous data transfer technology to hide the costs of CPU-GPU data transfer for resampling, ESD, and coherence estimation modules. After several optimizations, our GPU-accelerated modules (considering CPU-GPU transmission costs) achieves speedup ratios up to 157x, 166x, 145x, and 168x with respect to their single-threaded CPU counterparts. For a full frame S-1 image, our method reduces the computation time from 1415.32s to 8.59s. Moreover, our method is also validated in two case studies of the 2016 Mw6.2 Central Italy earthquake and 2018 Mw6.9 Leilani Estates earthquake caused by the Kilauea eruption in Hawaii.

The Internet of Things (IoT) has become a promising technology for addressing societal and industrial challenges by connecting geo-distributed and diverse devices to create smart systems worldwide. Nowadays, Distributed Database Systems (DDBS) are widely used in Internet of Things (IoT) frameworks to improve performance of massive data access. However, most recent caching techniques focus on collaborative caching and neglect the unbalanced workloads on hot data nodes, which may potentially become a bottleneck of latency-sensitive IoT services. To tackle this issue, we propose an adaptive multi-level caching strategy to solve the performance bottleneck caused by hot data access and therefore improve data access performance in DDBS. The essential idea of our strategy is to dynamically adjust cache resource allocation and cache size in different data nodes according to realtime access rate. In this way, more resources could be allocated to hot data node to speed up queries and eliminate the bottleneck. In addition, instead of the traditional Least Recently Used (LRU) algorithm, an efficient cache replacement algorithm is also proposed and implemented in our DDBS. The testbed experimental results indicate that the performance of DDBS with our adaptive multi-level caching strategy can be significantly improved by 20% compared with traditional strategies.

Existing algorithms can be automatically translated from software to hardware using High-Level Synthesis (HLS), allowing for quick prototyping or deployment of embedded designs. High-level software is written with a single main memory in mind, whereas hardware designs can take advantage of many parallel memories. The translation and optimization of memory usage, and the generation of resulting architectures, is important for high-performance designs. Tools provide optimizations on memory structures targeting data reuse and partitioning, but generally these are applied separately for a given object in memory. Memory access that cannot be effectively optimized is serialized to the memory, hindering any further parallelization of the surrounding generated hardware. In this work, we present an automated optimization method for creating custom cache memory architectures for HLS generated designs. Our optimization uses runtime profiling data, and is performed at a localized scope. This method combines data reuse savings and memory partitioning to further increase the potential parallelism and alleviate the serialized memory access, increasing performance. Comparisons are made against architectures without this optimization, and against other HLS caching approaches. Results are presented showing this method requires 72% of the number of execution cycles compared to a single-cache design, and 31% compared to designs with no caches.

Fortran coarrays are an attractive alternative to MPI due to a familiar Fortran syntax, single sided communications and implementation in the compiler. Scaling of coarrays is compared in this work to MPI, using cellular automata (CA) 3D Ising magnetisation miniapps, built with the CASUP CA library, https://cgpack.sourceforge.io , developed by the authors. Ising energy and magnetisation were calculated with MPI_ALLREDUCE and Fortran 2018 co_sum collectives. The work was done on ARCHER (Cray XC30) up to the full machine capacity: 109,056 cores. Ping-pong latency and bandwidth results are very similar with MPI and with coarrays for message sizes from 1B to several MB. MPI halo exchange (HX) scaled better than coarray HX, which is surprising because both algorithms use pair-wise communications: MPI IRECV/ISEND/WAITALL vs Fortran sync images . Adding OpenMP to MPI or to coarrays resulted in worse L2 cache hit ratio, and lower performance in all cases, even though the NUMA effects were ruled out. This is likely because the CA algorithm is network bound at scale. This is further evidenced by the fact that very aggressive cache and inter-procedural optimisations lead to no performance gain. The sampling and tracing analysis shows good load balancing in compute in all miniapps, but imbalance in communication, indicating that the difference in performance between MPI and coarrays is likely due to parallel libraries (MPICH2 vs libpgas) and the Cray hardware specific libraries (uGNI vs DMAPP). Overall, the results look promising for coarray use beyond 100k cores. However, further coarray optimisation is needed to narrow the performance gap between coarrays and MPI.

Rising demands for increased performance, lower energy consumption, connectivity and programming exibility are nowadays driving the platforms, so-called Multi-Processor Systems-on-Chips (MPSoCs). These platforms are composed of several processing elements, custom IP cores, and memories, all of which are in general interconnected by a Network-on-Chip (NoC). As attractive as these characteristics are, they introduce several security concerns, specially when applications with different trust and protection levels share resources. When a malicious software acquires access to an IP, it opens a door to external surveillance of the cache-memory, processing units and the NoC communication structure. The cache memory was already exploited by several authors in ASICs and Systems-on-Chips through Side-Channel Attacks (SCAs). In this work, we expand this concept, exploring the timing attacks on caches in the MPSoC scenario. We implement two well established attacks in the literature on a real hardware platform, the MPSoC Glass. Furthermore, we present the NoC as a novel vulnerability to increase attack e ciency, resulting in the Earthquake Attack. Results show that the attacks from literature can succeed inside the MPSoC, and obtain better results. Additionally, Earthquake improves the base attack by using the NoC timing attack, reducing the remaining attack complexity from 236:9 to 232 with 216:6 encryptions instead of 227:97.

Powering billions of devices is one of the most challenging barrier in achieving the future vision of IoT. Most of the sensor nodes for IoT based systems depend on battery as their power source and therefore fail to meet the design goals of lifetime power supply, cost, reliable sensing and transmission. Energy harvesting has the potential to supplant batteries and thus prevents frequent battery replacement. However, energy autonomous systems suffer from sudden power variations due to change in external natural sources and results in loss of data. The memory system is a main component which can improve or decrease performance dramatically. The latest versions of many computing system use chip multiprocessor (CMP) with on-chip cache memory organized as array of SRAM cell. In this paper, we outline the challenges involved with the efficient power supply causing power outage in energy autonomous/self-powered systems. Also, various techniques both at circuit level and system level are discussed which ensures reliable operation of IoT device during power failure. We review the emerging non-volatile memories and explore the possibility of integrating STT-MTJ as prospective candidate for low power solution to energy harvesting based IoT applications. An ultra-low power hybrid NV-SRAM cell is designed by integrating MTJ in the conventional 6T SRAM cell. The proposed LP8T2MTJ NV-SRAM cell is then analyzed using multiple key performance parameters including read/write energies, backup/restore energies, access times and noise margins. The proposed LP8T2MTJ cell is compared to conventional 6T SRAM counterpart indicating similar read and write performance. Also, comparison with the existing MTJ based NV-SRAM cells show 51–78% reduction in backup energy and 42–70% reduction in restore energy.

A Translation Lookaside Buffer (TLB) is a type of memory cache that is used to store recent translations of virtual to physical memory to reduce the access latency. Every time the processor accesses the virtual memory, it must be translated to the corresponding physical address, so the number of accesses to the TLB is high. Consequently, soft errors affecting the TLB can lead to hard fault, silent data corruption, and system freeze by corrupting its content. Many studies have proposed to provide protection for the Content Addressable Memory (CAM), which is a part of a TLB that stores the VPNs, but these protection techniques in most cases do not cover the case of multiple errors. This paper presents an efficient, fast and high error coverage approach to improve the reliability of TLB against Multiple Bit Upsets (MBUs) by considering the performance improvement with a low-cost overhead.

Measurement-Based Probabilistic Timing Analysis (MBPTA) facilitates the analysis of complex software running on hardware comprising high-performance features. MBPTA also aims at preventing additional analysis costs for timing analysis techniques and preserving the confidence on derived WCET estimates. Cache behavior has a deep influence on WCET estimates and hence on “the amount of software” that can be consolidated onto a single hardware platform. Deterministic replacement policies such as LRU (Least Recently Used) and NMRU (Non-Most Recently Used) have systematic pathological cases that may lead to high execution times and WCET estimates. Instead, random replacement (RR) decreases pathological cases probability, at the cost of temporal locality. We present two new MBPTA-amenable replacement policies that completely remove the presented pathological cases. The first policy, Random Permutations (RP) preserves higher temporal locality than RR; while the second, NMRU Random Permutations (NMRURP), also protects the Most Recently Used line from eviction. Both proposed policies build upon restricted random replacement choices. Our simulation evaluation (validated against a real prototype) using the Mälardalen benchmarks and a case study shows that RP and NMRURP deliver both high average performance (within 1% of LRUs and NRMU performance) and tight WCET estimates 11% and 24% lower than those of RR., This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015-65316-P, the European Research Council (ERC) under the European Union's Horizon 2020 research and innovation programme (grant agreement No. 772773) and the HiPEACH Network of Excellence. Pedro Benedicte and Jaume Abella have been partially supported by the MINECO under FPU15/01394 grant and Ramon y Cajal postdoctoral fellowship number RYC-2013-14717 respectively.

Memory footprint is a metric for quantifying data reuse in memory trace. It can also be used to approximate cache performance, especially in shared cache systems. Memory footprint is acquired through memory footprint analysis (FPA). However, its main limitation is that, for a memory trace of n accesses, the all-window FPA algorithm requires O(n3) time. Therefore, in this paper, we propose an analytical algorithm for FPA, whereby the average footprints are calculated in O(n2). The proposed algorithm can also be employed for window distribution analysis. Moreover, we propose a framework to enable the application of FPA to GPU kernels and model the performance of L1 cache memories. The results of experimental evaluations indicate that our proposed framework functions 1.55X slower than the Xiang’s formula, as a fast average FPA method, while it can also be utilized for window distribution analysis. In the context of FPA-based cache performance estimation, the experimental results indicate a fair correlation between the estimated L1 miss rates and those of the native GPU executions. On average, the proposed framework has 23.8% error in the estimation of L1 cache miss rates. Further, our algorithm runs 125X slower than the reuse distance analysis (RDA) when analyzing a single kernel. However, the proposed method outperforms RDA in modeling shared caches and multiple kernel executions in GPUs.

In this paper, we investigate the system model of random multi-user multi-UAV relay networks, where the transmission can be overheard by multiple eavesdroppers. We consider the random networks where the users, UAV relays and eavesdroppers arrive at the network subject to the homogeneous Poisson Point Process (PPP). Cache is equipped at UAV relays and users, and can pre-storage part of contents, which can help reduce the information leakage. Hence, it is of vital importance to design an effective secure probabilistic caching strategy to ensure the security of content transmission by combining the cache strategy and the physical-layer security in the presence of eavesdroppers. To this end, we first design the caching placement at users and UAV relays by taking into account four transmission schemes. We then analyze the secure performance of the caching placement by analyzing the expression of secure cache throughput. To maximize the secure cache throughput, we further optimize the probabilistic caching strategy by using the heuristic algorithm. Numerical results and discussion are provided to demonstrate that the proposed probabilistic caching strategy outperforms the conventional most popular content (MPC) and equal probability content (EPC) cache strategies, and the system secure performance can be improved by increasing the cache size and the intensity of UAV relays and users.

In developing countries, it is often difficult to use web content for e-learning because Internet accessing is unavailable or limited. To support education in such a situation, the authors previously proposed a system that uses a delayed update-tolerant web cache server and a wireless LAN. This system stores e-learning webpages requested by free school children in a cache memory, which is then carried to the free school so that the children can access the webpages in an off-line environment. The present paper proposes a cache deletion algorithm that reflects children’s requests for content retention in the cache server. It is called a user-oriented least recently used (LRU) algorithm. We have developed an experimental system that implemented this algorithm and carried out a learning experiment under conditions that simulated actual usage. We compared the proposed algorithm with existing cache deletion algorithms, including the least recently used (LRU), the least frequently used (LFU) and the least frequently recently used (LFRU) algorithms, in terms of the frequently accessed leaning cache retention rate.

In this study, we designed a KM-Cluster-based pattern adaptive prefetching mechanism for the last-level cache structure to support real time big data management. The goal is to predict future memory access patterns aggressively and accurately through a new self-learning prefetching engine model. The pattern adaptive last-level cache consisted of three major parts: the last-level cache, the first-level prefetching buffer (FLPB) and the second-level prefetching buffer (SLPB). The SLPB efficiently manages the history records of cache blocks evicted from the last-level cache through a self-learning mechanism. A K-means clustering algorithm is used as an SLPB prefetching scheme. Hybrid main memory is constructed using a small portion of the DRAM buffer space and primarily NAND-Flash memory space. The overall performance of our proposed model is evaluated for OpenStack Swift and in-memory database application-Redis. Experimental results show that the proposed architecture reduces the total execution time by 20.96% and power consumption by 31.9% compared to the same last-level cache size with no SLPB structure.

A increasing barrier in the development of the future generation of reliable microprocessors has secure memory on chip against soft bugs.Present efforts primarily focused on improving cache data set performance.A tag array also needs massive production efficiency for soft factual errors for its vital significance for caching entry accuracy.Using the memory access address location, it is recommended to repeat the most recent access to tag documents in the tiny tag duplication buffer (TRB) in order to maintain the tag list skill integrity in the cache memory.

The limitation of CMOS to operate under 25nm is a major concern, which is viewed in this paper. Also, scaling issues like leakage current, lower carrier mobility, higher junction capacitance limits the transistor operation is discussed. At lower voltage values, CMOS productive decreases drastically, which reflects on the performance of the circuit to achieve its criteria’s. In the present-day scenario of electronic industry, the speed of the processor is increasing, the urge for speed cache memory is also increasing. In cache memory design, SRAM cell is mainly used, CMOS SRAM Cells are producing more delay and also limitations like mentioned above. Therefore, an alternative preferred choice for SRAM Cells is FinFET, which increases the speed of the Cell by avoiding limitations caused by the bulk CMOS. By considering the advantages of the FinFET, SRAM Cells are implemented in Cadence virtuoso using FinFET 18nm Spectre. In this paper, standard SRAM Cells like 7T, 8T, 9T, and 1oT are simulated and parameters like power, delay, power delay product (PDP), energy-delay product (EDP) are calculated and respective values are presented by varying the voltage (V). SRAM Cells behavior under different voltages is graphically represented. CMOS SRAM Cell values have been taken from previous works of SRAM. By comparing the parameters, a drastic increase in the speed of the FinFET SRAM Cells can be observed over CMOS SRAM Cells.

On modern hardware architectures, the performance of Flux Reconstruction (FR) methods can be limited by memory bandwidth. In a typical implementation, these methods are implemented as a chain of distinct kernels. Often, a dataset which has just been written in the main memory by a kernel is read back immediately by the next kernel. One way to avoid such a redundant expenditure of memory bandwidth is kernel fusion. However, on a practical level kernel fusion requires that the source for all kernels be available, thus preventing calls to certain third-party library functions. Moreover, it can add substantial complexity to a codebase. An alternative to full kernel fusion is cache blocking. But for this to be effective, CPU cache has to be meaningfully big. Historically, size of L1 and L2 caches prevented cache blocking for high-order CFD applications. However in recent years, size of L2 cache has grown from around 0.25 MiB to 1.25 MiB, and made it possible to apply cache blocking for high-order CFD codes. In this approach, kernels remain distinct, and are executed one after another on small chunks of data that can fit in the cache, as opposed to on full datasets. These chunks of data stay in the cache and whenever a kernel requests access to data that is already in the cache, memory bandwidth is conserved. In this study, a data structure that facilitates cache blocking is considered, and a range of kernel grouping configurations for an FR based Euler solver are examined. A theoretical study is conducted for hexahedral elements with no anti-aliasing at p = 3 and p = 4 in order to determine the predicted performance of a few kernel grouping configurations. Then, these candidates are implemented in the PyFR solver and the performance gains in practice are compared with the theoretical estimates that range between 2.05x and 2.50x. An inviscid Taylor-Green Vortex test case is used as a benchmark, and the most performant configuration leads to a speedup of approximately 2.81x in practice.

With the continuous growth in the amount of data generated in the edge-cloud environment, security risks in traditional centralized data management platforms have been concerned. Blockchain technology can be applied to guarantee safety and information transparency in data caching and trading processes. Therefore, a blockchain-based secure cost-aware data caching scheme is proposed to optimize the placement and prevent the tampering of cache data. In this scheme, under the constraints of transmission cost, edge cache size, a quantum particle swarm optimization (QPSO) algorithm is used to solve the data cache placement problem with the greatest content caching gain. A blockchain-based secure decentralized data trading model is proposed to solve the trust problem among the buyers, sellers, and agent nodes and increase incentives for users to trade data. A double auction mechanism is used to maximize social welfare. The experimental results reveal that the proposed data caching and trading scheme can reduce the data transmission cost, improve the cache hit ratio, and maximize social welfare.

We present a cache-efficient parallel algorithm for the sequence alignment with gap penalty problem for shared-memory machines using multiway divide-and-conquer and not-in-place matrix transposition. Our r−way divide-and-conquer algorithm, for a fixed natural number r ≥ 2 , performs Θ ( n 3 ) work, achieves Θ ( n log r ⁡ ( 2 r − 1 ) ) span, and incurs O ( n 3 / ( B M ) + ( n 2 / B ) log ⁡ M ) serial cache misses for n > γ M , and incurs O ( ( n 2 / B ) log ⁡ ( n / M ) ) serial cache misses for α M n ≤ γ M , where, M is the cache size, B is the cache line size, and α and γ are constants.

In this paper, we propose a cache replacement approach for Fog applications in Software Defined Networks (SDNs). Our approach depends on three functional factors in SDNs. These three factors are: age of data based on periodic request, popularity of on-demand requests, and the duration for which the sensor node is required to operate in active mode to capture the sensed readings. These factors are considered together to assign a value to the cached data in a software-defined network in order to retain the most valuable information in the cache for longer time. The higher the value, the longer the duration for which the data will be retained in the cache. This replacement strategy provides significant availability for the most valuable and difficult to sense data in the SDNs. Extensive simulations are performed to compare our approach against other dominant cache replacement policies under varying circumstances such as data popularity, cache size, network load, and connectivity degree.

usc Refereed/Peer-reviewed By shrinking the transistors' dimensions, some aging phenomena effects that were negligible in previous technologies have become the most serious reliability threats. The most important aging process is Bias Temperature Instability (BTI). This phenomenon dissociates the chemical bonds between the silica lattice and hydrogen at the interface between the gate insulator and the transistor channel. The SRAM structures are vulnerable to BTI due to the long stress time on the transistors of this structure during normal system operations. Regardless of the stored values on the SRAM cells, the cross-coupled structure of this cell leads to continuous stress on at least two transistors of the cell at a given time. To mitigate the aging of the SRAM structures, like cache memories, there are many aging avoidance and aging mitigation techniques in the literature on this topic. However, the overheads or the efficiency thereof are not tolerable in many cases. This paper proposes an aging mitigation mechanism for cache memories by exchanging the values that are periodically stored in data and instruction caches. The results show that while the area and performance overheads of the proposed mechanism are negligible (less than 1%), the average stress time on the cache memories decreases by 2.39×, which prolongs the Mean Time to Failure (MTTF) of the memory structure by 1.91×.

In user-centric network (UCN), potential serving small base stations (SBSs) of user equipment (UE) form a dynamic SBS group (SBSG). Cache space and transmission resource of potential serving SBSs can be considered as an entity, but joint cache-level and transmission-level cooperation of UCN has not been analyzed in literature. This paper proposes dynamic hierarchical cache-aided transmission cooperation (CATC) in UCN, and derives semi-closed expressions of caching coverage, per-user throughput, and delay using stochastic geometry. Specifically, hierarchical CATC is dynamic since SBSG changes constantly, where UE utilizes increased aggregate cache space of potential serving SBSs by searching the contents in SBSG, and interference is coordinated among SBSs within SBSG. If not accessible in SBSG, the contents are searched in serving macro base station (MBS) and other SBSs managed by serving MBS to overcome limited cache size at SBSG. Moreover, SBSs cooperatively increase content diversity in the new content eviction policy (processed-least recently used (P-LRU)). The analysis reveals the tradeoff between coverage and throughput, for although hierarchical CATC increases hit ratio and caching coverage, per-user MBS throughput is constrained due to increased load. The analytical results are verified through simulations, and show that total and SBS caching coverage are improved by 53% and 81% respectively (when cache size of SBSs equals 10), compared to state-of-art user-centric transmission scheme.

Simultaneous Multi-Threading (SMT) is a processor design technique that supports concurrent execution of instructions from multiple threads in every cycle by sharing the key datapath components. In the SMT architecture, the shared resources normally include the physical register file, Issue Queue (IQ), functional units, write buffer and the cache memory. Efficient utilization of the shared resources is critical to achieving high-performance gain. The physical rename register file is one of the most critical shared resources in the SMT architecture due to its being located at forefront of the pipeline stages. The inter-thread sharing of the physical registers reduces the number of registers required in the SMT processors than would have been needed in deploying multiple superscalar processors to achieve a similar throughput. However, due to the nature of sharing, an overwhelming occupancy of the physical register file by any slower threads can lead to a shortage of registers available for the other threads in the system and thus degrade the overall performance. In this paper, we propose an intelligent fetching algorithm for efficient management of the shared physical register file. Even though the primary focus of this paper is to manage the physical register file effectively, it indirectly controls the other shared resources downstream in the pipeline as well. The main goal of this paper is to propose a simple resource management scheme capable of achieving a considerable performance gain that neither incurs a substantial processing or hardware overhead for practical implementation nor requires modifications in the other pipeline stages. We demonstrate that temporarily suspending the slow threads from the system in the fetch stage can improve the overall system performance by a significant margin. An improvement of up to 63% and 68% is achieved when the proposed scheme is applied to the 4-threaded and the 8-threaded system respectively. The throughput of an 8-threaded system with 320 register file entries is significantly higher than the performance of default system with 416 register entries indicating a resource saving of 60%.

In this paper we present some preliminary results in the field of computer systems management with relation to Tsallis thermostatistics and the ubiquitous problem of hardware limited resources. In the case of systems with non-deterministic behaviour, management of their resources is a key point that guarantees theirs acceptable performance and proper working. This is very wide problem that stands for many challenges in financial, transport, water and food, health, etc. areas. We focus on computer systems with attention paid to cache memory and propose to use an analytical model that is able to connect non-extensive entropy formalism, long-range dependencies, management of system resources and queuing theory. Obtained analytical results are related to the practical experiment showing interesting and valuable results.

Mobile (third-generation) sequencing technologies, including Oxford Nanopore’s MinION and SmidgION, have the benefit of outputting long sequence reads (up to hundred thousands of bases) in a portable manner. These sequencing devices fit in the palm of a hand and only require a USB outlet. Unfortunately, the development of data analysis tools for these technologies is in a nascent stage, impeding on the portability of these devices. The objective of this work is to introduce an out-of-core approach to port Nanopore analytics on mobile devices such as tablets or smartphones, often used in extreme experimental settings with special ergonomics needs and ease of sterilization. In this paper, we present a serial k-mer parser/counter for FAST5 files, and a de Bruijn graph construction method which can run on a hand-held device. In order to accomplish this portability we develop novel cache oblivious data structures and out-of-core chunked processing methods. Our toolset, which we refer to as Nanopore Portable Analytics Library (NanoPAL), wase implemented in ISO C++ v.14 and compiled for Android devices. Using MinION data (Zaire Ebolavirus species and others), we evaluate the time required to parse and build the de Bruijn graph with respect to the file sizes and RAM allocation. These metrics were compared to those of minimap/miniasm. On an LG Nexus 5 with 2GB or RAM, 2MB L2 cache and 16GB storage, the out-of-core NanoPAL is able to process FAST5 files at about 30 minutes per 0.5 GB, creating sorted k-mer and de Bruijn graph files. The recompiled minimap/miniasm tool cannot complete FAST5 files larger than 170MB. In conjunction with base calling/error correction, and with addition of assembly procedures downstream, NanoPAL can be effectively used to perform analyses of MinION/SmidgION data locally on a mobile device.

It is important for network operators to carry out traffic and application characterization to gain insights into the activity of their networks. Several studies proposed methods that extract features from network traffic to characterize it, or to classify the application that produced it, based on a “man in the middle” network interception point that can analyze the entire network traffic of an organization. This network topology, however, is increasingly becoming irrelevant, due to mobile and remote traffic joining the corporate network by passing through VPN channels or relay networks. In this work we propose an edge-oriented lightweight traffic characterization method, based on measuring contention on the last-level CPU cache. In contrast to previous traffic characterization methods, which track network traffic from a central location, our method performs measurements directly on user machines, using an unprivileged JavaScript-based webpage. Our evaluation shows that the accuracy of our cache-based method is equivalent to that of network-based methods, both over VPN and over non-VPN networks.

In recent years, researches focus on addressing the query bottleneck issue using semantic cache. However, the challenges of this method are how to increase cache hit ratio, decrease the query processing time, and address cache consistency issue. In this paper, we construct segment access-aware dynamic semantic cache for relational databases. Some definitions of semantic segment, probe query, and remainder query are proposed to describe the semantic cache. Then, estimation of the query result is proposed. Next, cache access algorithm of our proposed segment access-aware dynamic semantic cache is presented in case of cache exact hit, cache extended hit, cache partial hit and cache miss. Cache item with effective lifecycle tag is proposed to address cache consistency issue. Finally, experimental results show that this approach performs better than regular semantic cache and decisional semantic cache.

In this paper, we propose a Cognitive Caching approach for the Future Fog (CCFF) that takes into consideration the value of the exchanged data in Information Centric Sensor Networks (ICSNs). Our approach depends on four functional parameters in ICSNs. These four main parameters are: age of the data, popularity of on-demand requests, delay to receive the requested information and data fidelity. These parameters are considered together to assign a value to the cached data while retaining the most valuable one in the cache for prolonged time periods. This CCFF approach provides significant availability for most valuable and difficult to retrieve data in the ICSNs. Extensive simulations and case studies have been examined in this research in order to compare to other dominant cache management frameworks in the literature under varying circumstances such as data popularity, cache size, data publisher load, and node connectivity degree. Formal fidelity and trust analysis has been applied as well to emphasize the effectiveness of CCFF in Fog paradigms, where edge devices can retrieve unsecured data from the authorized nodes in the cloud.

Computer system and network performance can be significantly improved by caching frequently used information. When the cache size is limited, the cache replacement algorithm has an important impact on the effectiveness of caching. In this paper we introduce time-to-live (TTL) approximations to determine the cache hit probability of two classes of cache replacement algorithms: h-LRU and LRU(m). These approximations only require the requests to be generated according to a general Markovian arrival process (MAP). This includes phase-type renewal processes and the IRM model as special cases. We provide both numerical and theoretical support for the claim that the proposed TTL approximations are asymptotically exact. In particular, we show that the transient hit probability converges to the solution of a set of ODEs (under the IRM model), where the fixed point of the set of ODEs corresponds to the TTL approximation. We use this approximation and trace-based simulation to compare the performance of h-LRU and LRU(m). First, we show that they perform alike, while the latter requires less work when a hit/miss occurs. Second, we show that as opposed to LRU, h-LRU and LRU(m) are sensitive to the correlation between consecutive inter-request times. Last, we study cache partitioning. In all tested cases, the hit probability improved by partitioning the cache into different parts each being dedicated to a particular content provider. However, the gain is limited and the optimal partition sizes are very sensitive to the problem's parameters. (C) 2017 Elsevier B.V. All rights reserved.

GPUs provide megabytes of registers and shared memories to maintain the contexts for thousands of threads and enable fast data sharing amongst threads of a thread block, respectively. Besides, GPUs employ L1 cache to provide the high bandwidth service for memory requests. However, the average L1 cache capacity per thread is very limited, resulting in cache thrashing which in turn impairs the performance. Meanwhile, many registers and shared memories are unassigned to any warps or thread blocks. Moreover, registers and shared memories that are assigned can be idle when warps or thread blocks are finished. Exploiting the above insights, we propose Virtual-Cache to cost-effectively increase the effective size of L1 cache by utilizing the unassigned and released registers and shared memories as cache-lines in this paper. Specifically, we leverage the unassigned registers and shared memories to serve cache requests directly. Regarding the registers assigned to a warp, they can work as cache-lines after the warp completes the execution and before they are accessed again by a new launched warp. Regarding the shared memories of a thread block, they are enabled to serve cache requests when the thread block is finished till they are referenced by shared memory instructions of the relaunched thread block. The register file, shared memory and L1 cache are physically independent but logically unified as a large virtual cache with redesigned cache-line management. We develop the control and data path for the register file, making the register file accessible for cache requests by borrowing an operand collector to serve the cache requests. We also expand the control and data path for the shared memory to serve the cache requests. Our evaluation results show that Virtual-Cache makes the performance improved by 28% over the previously proposed cache management technique for cache-sensitive applications.

This paper presents an area and energy-efficient non-volatile Last-level Cache (LLC) using a STT-MRAM based on a state-of-art perpendicular magnetic tunnel junction (pMTJ) and an Vertical Gate-All-Around Field-Effect Transistor (GAA-FET). This work presented, in this article is carried out from device to circuit, architecture and up to the system level. A detailed analysis of STT-MRAM has been presented by comparing an Vertical GAA-FET (GA) with a bulk-FET (B) at cell level. It is observed that GA-STT-MRAM is advantageous and offers 93.10% and 60% reduction in leakage-power dissipation and area, respectively over B-STT-MRAM. Furthermore, at architecture level, 20% to 80% reduction in sizes of LLCs (ranging from 512 KB to 64 MB) is observed by using GA-STT-MRAM and around 80.78% leakage power reduction is achieved in comparison to SRAM based LLCs. In addition to the architecture level, GA-STT-MRAM is found to have 83.26% and 39.40% energy reduction compared to a B-STT-MRAM and a conventional SRAM, respectively at system level. The GA-STT-MRAM proves to be a more promising candidate to replace conventional semiconductor based LLC for next-generation energy-efficient microprocessors having on-chip non-volatility.

Our goal for this study is to enable the development of discrete deep neural networks (NNs), some parameters of which are discretized, as small-footprint and fast NNs for acoustic models. Three essential requirements should be met for achieving this goal; 1) the reduction in discretization errors, 2) implementation for fast processing and 3) node-size reduction of DNNs. We propose a weight-parameter model and its training algorithm for 1), an implementation scheme using a look-up table on general-purpose CPUs for 2), and a layer-biased node-pruning method for 3). The first proposed method can set proper boundaries of discretization at each NN node, resulting in reduction in discretization errors. The second method can reduce the memory usage of NNs within the cache size of the CPU by encoding the parameters of NNs. The last method can reduce the network size of the quantized DNNs by measuring the activity of each node at each layer and pruning them with a layer-dependent score. Experiments with 2-bit discrete NNs showed that our training algorithm maintained almost the same word accuracy as with 8-bit discrete NNs. We achieved a 95% reduction of memory usage and a 74% increase in speed of an NN’s forward calculation.

For cache analytical modeling, the stack distance theory is widely utilized to predict LRU-cache behaviors. Typically, the stack distance histogram collecting is implemented by profiling memory references. However, the profiled memory references merely reflect instruction fetching and load/store executions, which only represent the memory accesses to first-level (L1) caches. That is why these traces cannot be applied directly to construct stack distance histograms for downstream (L2 and L3) caches. Therefore, this paper proposes a stack distance probability model to extend the stack distance theory to the multi-level LRU cache behavior predictions. The inputs of our model are the L1 cache stack distance histograms and the multi-level LRU cache configurations. The outputs are the L2 and L3 cache stack distance histograms, with which the conflict misses in L2 and L3 caches can be quantified quickly and precisely. 15 benchmarks chosen from Mobybench 2.0, Mibench I and Mediabench II are used to evaluate the accuracy of our model. Compared to the simulation results from Gem5 in AtomicSimpleCPU mode, the average absolute error of predicting cache misses in the I/D shared L2 cache is less than 5% while that of estimating the L3 cache misses is less than 7%. Furthermore, contrast to the time overhead of Gem5 AtomicSimpleCPU simulations, our model can speed up the cache miss prediction about x100 on average.

eDRAM cells have been considered as a promising alternative to conventional SRAM cells and already adopted in commercial processors. However, eDRAM cells need to be refreshed periodically, resulting in non-negligible energy and performance overhead. Moreover, under process variations, retention time of eDRAM cells exhibits non-uniform distributions. This phenomenon affects both manufacturing yield and eDRAM refresh burden. In this paper, we first analyze eDRAM module (cache) yield and retention time failure patterns under process variations. Based on our analysis, we disclose most of the failing cache lines have only one faulty cell and propose a cost-efficient technique to save those one-cell failing cache lines. Our technique maintains a one-cell failing line (OFL) buffer which manages the status of the one-cell failing cache lines. By effectively curing one-cell failing lines, our technique significantly improves manufacturing yield by up to 46.1% under the identical refresh intervals. In addition, our technique can be used to loosen refresh intervals with comparable yield. By using the loosened refresh intervals, our technique reduces energy per instruction and improves performance by up to 19.9% and 1.3%, respectively.

Multi-core mixed-criticality systems are complex solutions that provide benefits regarding lower power consumption, size, weight and cost and better performance and scalability, compared with single-core architectures. However, these systems where virtualization mechanisms such as hypervisors are used for integrating functionalities with different criticality levels into the same hardware platform and where on-chip and off-chip communication systems are implemented for communicating, imply certification challenges due to their complexity. Those challenges to certification are supported by the fact that today’s safety-related standard focus on single computing systems where spatial and temporal interferences are quite probable. Multi-core architectures enable sharing resources (e.g., cache memory, I/Os) between more than one processor at the same time, facilitating the appearance of interferences which may hinder the achievement of the spatial and temporal independences. This paper analyses the certification challenges in mixed-criticality systems and identifies some reusable generic solutions to overcome those challenges. The solutions presented in this paper are integrated into a safety wind turbine system that follows the design style introduced in European project DREAMS.

All Programmable System-on-Chip (APSoC) devices are designed to provide higher overall programmable flexibility and system performance at lower costs. Such characteristics make APSoCs very suitable and attractive for critical environments, such as the one encountered in the accelerators chain of the European Organization for Nuclear Research (CERN), where electronic components can be exposed to high-energy hadrons (protons, neutrons, pions), heavy ions, and other particles, at the same time. However, APSoCs may be prone to experience Single Event Effects (SEE). We investigate how the configuration of the Processing System (PS) influences the reliability of a FLASH-based APSoC. We experimentally study the differences in the radiation-induced error rate of the PS, under various configurations while executing an application. We also propose two approaches for increasing the reliability of programs running on the embedded processor. Furthermore, we analyze the sensitivity of the system taking into account not only the cross section, but also the system reliability and the Mean Workload Between Failures (MWBF). Preliminary results show that it is possible to double the performance and to increase the system reliability up to one order of magnitude by managing processor features such as cache memory usage, error correcting codes, and processor exception handlers.

This paper presents an approach based on software-based fault tolerance techniques applied at low abstraction level to detect SEU faults in register files of Graphics Processing Units. SEU faults have a major influence on such architectures, especially affecting register files and cache memory. In order to harden the system's register files, software-based techniques are presented and tuned to detect faults in vector, address, and predicate registers. A fault injection campaign at Register Transfer Level is performed on the register files using a G80 general purpose graphics processing unit running four case-study applications. Results show reduction in errors up to 100% and overhead costs in execution time up to 1.78 times the original values.

In this article, we analyze file access characteristics of smartphone applications and find out that a large portion of file data in smartphones are written only once. This specific phenomenon appears due to the behavior of SQLite, a lightweight database library used in most smartphone applications. Based on this observation, we present a new buffer cache management scheme for smartphone systems that considers non-reusability of write-only-once data that we observe. Buffer cache improves file access performances by maintaining hot data in memory thereby servicing subsequent requests without storage accesses. The proposed scheme classifies write-only-once data and aggressively evicts them from the buffer cache to improve cache space utilization. Experimental results with various real smartphone applications show that the proposed buffer cache management scheme improves the performance of smartphone buffer cache by 5%–33%. We also show that our scheme can reduce the buffer cache size to 1/4 of the original system without performance degradation, which allows the reduction of energy consumption in a smartphone memory system by 27%–92%.

Time dependent dielectric breakdown degrades the reliability of SRAM cache. A novel methodology to estimate SRAM cache reliability and performance is presented. The performance and reliability characteristics are obtained from activity extraction and Monte Carlo simulations, considering device dimensions, process variations, the stress probability, and the thermal distribution. Based on the reliability-performance estimation methodology, caches with various settings on associativity, cache line size, and cache size are analysed and compared. Experiments show that there exists a contradiction between performance and reliability for different cache configurations. Understanding the variation of performance and reliability can provide SRAM designers with insight on reliability-performance trade-offs for cache system design.