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The impact of the stem height of T-gate electrodes on the parasitic gate delay time in InGaAs high electron mobility transistors (HEMTs) is studied. Since T-gates with higher stem height make the parasitic gate capacitance smaller, the higher stem height is expected to minimize the parasitic gate delay. However, a systematic study using the devices with different stem height of T-gates reveals that the parasitic gate delay time decreases with the parasitic gate capacitance only at a drain voltage around the knee voltage and it becomes less sensitive to the parasitic capacitance by the T-gate when the device is operated in the deep saturation region at high drain bias voltage. This result suggests a design strategy for T-gate electrodes so that the tradeoff between the gate resistance and gate capacitance must be considered seriously in the devices for low-voltage applications, while one has more flexibility to use the T-gate electrode with a large head in the devices for high-voltage applications. [ABSTRACT FROM AUTHOR]

Abstract: The operation at frequencies above 100GHz of electronic devices like transistors has been achieved both by using high electron mobility III–V semiconductor materials or heterostructures and by implementing fabrication techniques which strongly reduce parasitic capacitances between the device terminals, without increasing series resistances. The technology has been applied on different GaN high electron mobility transistor epiwafers, and the devices performances analyzed under their DC and RF characteristics, outlining that further semiconductor material optimization is mandatory to fully benefit the sub ¼ micron Gate length for very high frequency operation advantage. [Copyright &y& Elsevier]

A new e-beam lithography method using stepping exposure was proposed to obtain a floating Y-gate for high electron mobility transistor (HEMT) application. The resist thickness shows good linearity with the exposure dose. An AlGaN/GaN HEMT device with 120 nm gate length was fabricated by this method. The device shows improved breakdown and frequency performance (fmax∙BV increased by 55%) compared to the traditional T-gate device. [Display omitted] • The stepping litho method shows a good linearity with exposure dose. • The Y-gate shows about 23° of dip angle. • The Y-gate improves the f t /f max and the BV of device at the same time. • The f max ∙BV of Y-gate device is improved 55% compared with T-gate device. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents two separate methods for the fabrication of 10nm footprint T-gates using a two-step gate process. We examine the limits of lithographic and pattern transfer processes using the exposure of ZEP520A resist by electron beam lithography, suitable development processes and subsequent pattern transfer by reactive ion etching of a silicon nitride layer on III–V substrates. In a second process, the dimensions of a larger initial feature are reduced using the deposition and etching of conformal silicon nitride. Both processes have yielded metallised gates with a footprint as small as 10nm and are suitable for incorporation into a HEMT process flow. [Copyright &y& Elsevier]

Abstract: In this paper analytical modeling for a novel three region gate dielectric engineered AlGaN/GaN Metal Insulator Semiconductor heterostructure field effect transistor (MISHFET) device architecture is presented which shows high transconductance and enhanced cut-off frequency at quarter micron gate lengths. Using a three region analysis along the horizontal direction in the gate dielectric region the expressions for transconductance and cut-off frequency of the device are obtained. It has been observed that using these gate dielectric schemes, improvements on device performance are observed over conventional MISHFET structures. Relative comparison of T and Γ-gate shaped structures is done with uniform gate dielectric profile and enhancement in microwave performance is observed. The proposed model is capable of modeling electrical characteristics like drain current, output conductance and threshold voltage of various other existent structures like uniform gate dielectric MISHFETs, HFETs and T-gate HFETs. The present model is based on closed form expression and does not involve any fitting parameter. The results obtained are compared with experimental data and show excellent agreement, thereby proving the validity of the model. [Copyright &y& Elsevier]

Abstract: This paper reports a new method for the fabrication of sub-25nm T-gates for high electron mobility transistors (HEMTs). For robust fabrication, it may be advantageous to employ a two-step process where the gate foot and head can be separately defined. The new process uses ZEP520A electron beam resist as a mask for SF6-based anisotropic reactive ion etching of ICP-deposited silicon nitride to define the gate foot. The gate head structure, defined in PMMA/LOR/UVIII, is then lithographically aligned to the gate foot. All electron beam lithography was performed using a Vistec VB6 UHR EWF tool. The design flexibility, mechanical stability, gate resistance and plasma-induced damage of this new method and its suitability for integration in a HEMT process flow are evaluated in this paper. This work has led to the high-yield fabrication of robust 22nm T-gates. [Copyright &y& Elsevier]

Recent advances in electron beam lithography have made possible the fabrication of pseudomorphic high electron mobility transistors (PHEMTs) with gate length well in the nanometer regime. This gate processes mostly require thin dielectric support layers in order to prevent collapse of gate head due to poor mechanical reliability in the narrow gate foot. However, this layer is a major cause for parasitic capacitance. In this paper, we have demonstrated the fabrication of a 70 nm foot print of the T-shaped gate by using a positive resist ZEP520/P(MMA-MAA)/PMMA trilayer by double exposure method without a thin dielectric supporting layer on the substrate. [Copyright &y& Elsevier]

This paper describes the use of a unique combination of an environmentally stable chemically amplified photoresist (UV113, Shipley) and a copolymer of methyl styrene and chloromethyl acrylate P(MS/CMA) resist (ZEP520, Zeon), without any additional intermediate layers, in the fabrication of high-resolution T-gates and Γ-gates. The two resists used are innocuous to each other during the designed process flow, providing flexibility, high resolution, greater throughput and ease of use. [Copyright &y& Elsevier]

This paper reports a simple route to fabricating T-gate like structures with footprint of 40 nm using a copper electroplating process and a single electron beam lithography step without the need for lift-off. To our knowledge, these are the smallest such structures demonstrated using this approach which could also be implemented straightforwardly using conventional stepper or nanoimprint lithography for low cost, high volume silicon compatible manufacture. [ABSTRACT FROM AUTHOR]

Abstract: In this paper we present design, fabrication and characterization of Schottky terahertz diodes. The diode is based on a Ti/n-GaAs junction with very low junction capacitance. T-gate technology, based on trilayer of electronic resists and electron-beam lithography, and air-bridge technique have been used to obtain Schottky diodes with cutoff frequency in the THz range. The device fabrication process is fully planar and suitable for integration in monolithic arrays for active spectroscopic imaging. [Copyright &y& Elsevier]