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We investigate the difference in the probability of latch-up occurrence in complementary metal–oxide–silicon (CMOS) circuits exposed to neutron radiation and total ionizing dose (TID), which are subsequently exposed to pulsed gamma rays. First, we irradiate three types of CMOS circuits in a reactor for neutron exposure and in a Co-60 unit for TID exposure respectively, which are then placed in a pulsed gamma-ray environment. The latch-up induced by pulsed gamma-ray irradiation is studied. Our experimental results indicate that the manifestation of the latch-up phenomenon is different among the devices after neutron irradiation and TID exposure, thereby indicating that the influences of neutron and TID exposures on the latch-up sensitivity are different. To understand how the latch-up sensitivity changes, we study a dynamic model for latch-up occurrence and analyse the influences of neutron and TID exposure using the model. Our results indicate that neutron injection reduces the susceptibility of latch-up occurrence, whereas TID exposure increases the latch-up occurrence susceptibility. Therefore, in the case of CMOS circuits exposed to pulsed gamma-ray irradiation, the latch-up threshold decreases with TID accumulation, but increases with neutron fluence augmentation. Interestingly, the latch-up threshold drops when the neutron fluence is sufficiently large, mainly because concomitant gamma rays in the reactor environment play an important role in affecting the threshold. [ABSTRACT FROM AUTHOR]

In this paper, a numerical description of the ruggedness of punch-through (PT) IGBTs under the unclamped inductive switching (UIS) has been proposed using two-dimensional (2D) simulations with the calibration to experimental results. The UIS capability is an important design factor of device structures for the purpose of screening defects produced during the wafer process. The local hot spot due to the current filament three-dimensionally (3D) distributed over the chip area requires 3D simulations to reproduce the current density of the filament and its behavior leading to the device destruction; however, it is difficult to simulate such a large area with an appropriate mesh size and a boundary condition. To provide a possible solution of this technical issue, 2D simulations using large scale multi-cell structures with the increased current density has been proposed to reproduce experimental results without resorting to 3D simulations. With this approach, not only destructive phenomena including the UIS ruggedness and the latch-up failure mode have been reproduced, but also the device internal state leading to the destruction has been revealed. The spatial distribution of the electric potential and the lateral electric field during the UIS condition is shown to be a key role determining the current filament width and the UIS ruggedness. Besides, the high frequency oscillation of the collector voltage during the UIS observed by experiments has been analyzed and has found to be related with the hopping motion of the current filament from a cell to its neighboring cell of the device. [ABSTRACT FROM AUTHOR]

We investigate a novel lateral diffused metal-oxide semiconductor (LDMOS) device embedded in silicon controlled rectifier (SCR) and resistance-capacitance circuit (LDMOS-SCR-RC). The internal RC-coupling effect helps to increase the holding current ( I h ), resulting in the enhanced latch-up immunity of electrostatic discharge (ESD) protection device in high voltage integrated circuits (HV ICs). Transmission line pulse testing results show that the proposed LDMOS-SCR-RC has the largest I h and smallest trigger voltage ( V t 1 ), comparing to the conventional LDMOS-SCR and LDMOS-SCR embedded a resistance. When key parameters such as the gate-length and resistance are optimized, the I h increases further from 1.1 A to 1.5 A, while the V t 1 changes insignificantly. The detailed internal mechanism of LDMOS-SCR-RC with regard to key parameters is analyzed numerically by the SENTAURUS simulation. Results confirm that the increased I h is mainly due to the enhanced RC-coupling effect. Finally, DC measurements conducted with a semiconductor curve tracer also confirm that the LDMOS-SCR-RC with small device area is effective for avoiding latch-up risks. The optimized LDMOS-SCR-RC provides a useful latch-up immune ESD protection solution for HV ICs input/output ports. [ABSTRACT FROM AUTHOR]

An analytical model of transient latch-up in CMOS transmission gate induced by laser is established. The time-dependent current characteristics of the parasitic silicon controlled rectifier (SCR) under different injected photocurrent are illustrated. The model analyzes the trigger conditions for latch-up and describes the dynamic process varying with time. The photocurrent threshold causing latch-up under different pulse widths and repetition frequencies is obtained, which agrees well with the experimental results reported in the literature. [ABSTRACT FROM AUTHOR]

Abstract: Formation of lateral thin-film 700-V insulated-gate bipolar transistors (IGBTs) on Si-semiconductor-on-insulator (Si-SOI) substrates by using retrograde p-well double implantation scheme has been proposed. With a low thermal budget for p-well formation, retrograde high-energy boron implantation is employed to cause a high dopant concentration in the bulk region, and additional low-energy boron implantation is carried out for alleviating the surface punch-through of MOSFET (metal-oxide-semiconductor-field-effect-transistor) structure. As compared to the conventional p-well formation process, the retrograde double implantation scheme can lead to better latchup immunity, due to a considerably higher dopant concentration and thus lower well resistance in the p-well bulk region. In addition, owing to a lower surface dopant concentration, the retrograde double implantation scheme can lead to better on-state characteristics than the conventional process, while achieving comparable blocking voltage. [Copyright &y& Elsevier]

Abstract: The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip electro-static-discharge (ESD) protection. The device has a small area in requirement robustness in comparison to gate-grounded NMOS (ggNMOS). The proposed ESD protection device is designed in 0.25μm CMOS technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 3.8V and a high trigger current of greater than 120mA. The robustness has measured to HBM 8kV (HBM: human body model) and MM 400V (MM: machine model). The proposed device has a high-level It2 of 52mA/μm approximately. [Copyright &y& Elsevier]

Abstract: Latch-up effects in two stage cascaded CMOS digital inverters due to high power pulsed electromagnetic interference, are reported. Latch-up was observed to occur at and above 25.5dBm of pulsed interference at frequencies of 1.23GHz and 4GHz. When a latch-up event occurred, the devices failed to respond to the input logic signal even after the pulsed interference was removed. Devices required to be reset to return to normal operation. Latch-up for pulsed interference at the higher frequency of 4GHz occurred at higher power levels, indicating a suppression of the interference effects at higher frequencies due to the by-pass path effects provided by the intrinsic device capacitances. High power interference induced excess carriers and the corresponding body currents that activated the parasitic bipolar transistor action were found to play a key role in triggering the latch-ups, and are proposed here as the main mechanism for the upsets. The parasitic resistances R1 and R2 for the cascaded inverters were calculated to be 4.3 and 2.8kΩ, respectively, and the corresponding excess body currents triggering the latch-ups were 0.163 and 0.25mA, respectively. [Copyright &y& Elsevier]

Abstract: This paper investigates the performance of single and multiple junction isolation structures for smart power IC’s with regards to transient carrier injection. Both, single and multiple isolation structures are produced using a standard CMOS process all using the same surface area. The devices are based on different active junction isolation principles and it is shown that combinations of these devices can significantly improve the blocking characteristics of the isolation without an increase in surface area. It is shown that the transient current rejection of the devices is markedly different from their dc blocking characteristics. Considerations for the design of efficient isolation structures are discussed. [Copyright &y& Elsevier]

Abstract: In this paper, a new lateral insulated gate bipolar transistor (LIGBT) structure is proposed to suppress substrate currents in a junction isolated technology by using two buried layers on top of each other. This structure not only allows to reduce the substrate to anode current ratio to less than 10−7, it also yields a device with a large safe operating area and a fast turn-off. Because of the two buried layers, the proposed LIGBT can be used as a floating (above substrate potential) device. Furthermore, the LIGBT is introduced in an existing 80 V smart power technology without the costly need of defining new layers. It has also been shown that the proposed LIGBT can compete with vertical DMOS (VDMOS) devices when used as a large driver. Together with an equivalent circuit, two dimensional simulation has been used to explain the observed device’s substrate current behaviour. [Copyright &y& Elsevier]

The paper reports on a set of measurements which were carried out to test the influence of single event upset (SEU) effects on the performance of the VA1TA chip, the front end read-out electronics unit of the upgraded silicon vertex detector for the Belle spectrometer. In addition, the functionality of the SEU correction circuits in the chip were examined. [Copyright &y& Elsevier]

The future LHC particle accelerator will use a large number of cryogenic sensors and actuators, most of which are located inside the machine tunnel and therefore in a radiation environment. These elements will communicate through a fieldbus. This paper reports the irradiation study carried out on WorldFIP fieldbus communication system.A digital communication system based on WorldFIP fieldbus protocol has been implemented and single event effects and total ionizing dose radiation tests have been performed on it. [Copyright &y& Elsevier]

Many challenges accompany the use of three-dimensional (3D) integrated circuits (ICs). Some of these challenges are design-related, while others are verification-related. In this paper, we focus on verification issues; more precisely, on advanced layout physical verification tasks, such as advanced latch-up design rule checks and candidate hot junction detection. We explain the differences and additional challenges as compared to conventional two-dimensional (2D) IC verification. We introduce a programmable checker to automate these verification challenges for complete 3D IC designs. The checker differentiates between external and internal inputs/outputs from the assembly level without using layout markers on the die level. It checks external latch-up design rules using a topology-aware analysis, and checks mixed voltage latch-up design rules using a voltage-aware analysis. It also detects candidate hot junctions, because their existence can cause damage if voltage rises too high and current is not sufficiently limited. A design is used to illustrate the different type of checks, and demonstrate how to set up required input constraints, share captured results/violations, and effectively debug results to overcome potential design weaknesses. • 2.5D/3D IC latch-up • 2.5D/3D IC hot junction detection • Automated verification • Calibre PERC [ABSTRACT FROM AUTHOR]