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Abstract The carrier recovery loops are important in carrier tracking approaches particularly in the presence of high dynamic stress on user receivers and noisy environment applications. The precise carrier tracking techniques are proposed in systems that are sensitive to carrier mismatches, such as terrestrial or satellite tracking systems. The fading phenomenon, phase and frequency step changes and high user dynamics are currently most important challenges in the development of robust carrier tracking systems. In this work, a novel Digital Phase Locked Loop (DPLL) is proposed using type-2 fuzzy logic controller to improve noise immunity and handling user dynamic in digital receivers with application customization capability. Due to fast and accurate decision-making by proposed fuzzy logic controller, optimal loop filter coefficients are generated for DPLL. The proposed DPLL is simulated with Xilinx System Generator Software and can be implemented on FPGA. In comparison to traditional approaches, proposed new DPLL shows better performance in response to phase step, frequency step and frequency ramp signals with acceptable settling time alongside minimum complexity in implementation and customization. [ABSTRACT FROM AUTHOR]

This paper presents a digital phase-locked-loop (DPLL) based on multi-output bang-bang phase detector (MOBBPD) with reused most significant bits (MSBs) of MOBBPD. The MOBBPD can be implemented simply while achieving the merits of both time-to-digital converter (TDC) and bang-bang phase detector (BBPD). The digital PLL's locking time can be reduced due to the multi-output comparing with the classical digital PLL's with standard BBPD. In order to further shorten the loop locking time, we propose to reuse the MSBs, which are trigged at the early stage of locking acquisition, such that the phase difference can quickly decrease. Because of its simple structure, the proposed DPLL can be designed without much effort. The prototype DPLL is fabricated in a standard 0.18-μm CMOS process. The measurement results show that the output clock frequency ranges from 0.768 to 1.344 GHz. The total measured power consumption is 4.7 mW and the measured locking speed is around 40 times faster than a typical design without reusing the MSBs at 1.024 GHz. [ABSTRACT FROM AUTHOR]

Angle tracking loop in airborne radar systems is vital in 3D joint tracking loops of range, velocity, and angle. This study concerns two angle tracking issues when an airborne digital array radar system tracks a maneuvering target: slow convergence, and a divergent issue of tracking errors at the final tracking phase. A new angle tracking loop called “constant coefficient angle tracking loop filter” (CCATLF) based on digital phase-locked loop (DPLL) is proposed. To improve tracking performance, a novel algorithm called “adaptive angle tracking loop filter” (AATLF) is also proposed based on CCATLF. In this algorithm, an adaptive equivalent loop noise bandwidth is derived to adjust with the angle by solving an optimization problem that involves angle measuring value and beam pointing. A theoretical error variance formula and stability analysis of the loop are also presented. Experiment results demonstrate that the proposed AATLF algorithm performs better, and is more effective and robust compared with other angle tracking algorithms. [ABSTRACT FROM AUTHOR]

Abstract: Nonlinear dynamics of a class of symmetric lock range digital phase-locked loops (SLR-DPLLs) has been investigated using nonlinear dynamical theoretical and computational tools. It has been observed that the system shows a period doubling route to chaos. For certain system parameters the loop exhibits intermittent behavior. The analytical bifurcation analysis shows that inspite of the broader frequency acquisition range than a conventional one the stability of the loop degrades appreciably when the input signal frequency is less than the nominal frequency of the digitally controlled oscillator. The system dynamics have been characterized by measuring the Lyapunov exponent and the correlation dimension. Further it has been shown that the stability range of a SLR-DPLL can be extended using a modified loop filter incorporating time delay feedback technique. The modified SLR-DPLL (MSLR-DPLL) with this additional derivative control along with the loop digital filter (LDF) shows faster convergence than the unmodified one for proper choice of system design parameters. Consequently, the MSLR-DPLL becomes more suitable for practical applications. [Copyright &y& Elsevier]

Abstract: A repetitive-Fuzzy PID and digital phase-locked loop (DPLL) integrating control strategy for High-Frequency(HF) inverter power supply is presented. The power modulation of HF-Inverter used repetitive-Fuzzy PID compound control,which can enhance the ability of the control system to withstand the parameter variations and nonlinear uncertain disturbances, and improve the dynamic characteristic of the control system; the DPLL was applied.to control the output frequency of HF-inverter,which reduce the losses of switching components and improve the efficiency of the power system. The experimental results show that the proposed control scheme can endow the HFinverter power supply with good steady state and dynamic performance and the power modulation control system can keep better precise control quality, high output power factor and verify the validity of the proposed integrated control strategy. [Copyright &y& Elsevier]