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In the field of high-performance chip designs, many applications have the ability to tolerate small errors through the use of approximate full adders. By appropriately reducing the corresponding precision, the performance of hardware implementation can be greatly improved. The adders are commonly applied in digital signal processors (DSP), communication systems, image processing, etc., to quickly complete addition estimation operations. This paper proposes the designs of 8 approximate adders and compares their performance with existing circuit structures. Simulation results demonstrate that the approximate adders proposed in the first group (i.e., LCAFA1∼LCAFA3) achieve an average area reduction of 21.44 % and an average delay reduction of 42.85 %. In the second group, the proposed approximate adders LCAFA4∼LCAFA8 achieve an average power reduction of 28.35 %, an average area reduction of 17.39 %, an average delay reduction of 84.25 %, and an average decrease in the power-area-delay product (PADP) of 68.26 %. [ABSTRACT FROM AUTHOR]

This paper first presents a double-node upset (DNU) protected and sextuple cross-coupled static-random-access memory (SRAM) cell, i.e., SCCS-18T, for aerospace applications. The cell can recover from each possible single-node upsets (SNUs) as well as partial DNUs due to its formed large feedback loop that can retain values and intercept errors. To improve DNU self-recoverability, an enhanced version of the SCCS-18T cell, namely SCCS-18T-EV, is proposed. Due to the new formed structure, the SCCS-18T-EV can recover from more DNUs. Since parallel access transistors are used, the proposed cells have optimized read/write performance. Simulation results demonstrate the node-upset tolerance as well as the optimized operation performance of the proposed SCCS-18T and SCCS-18T-EV cells compared to existing SRAM cells. [ABSTRACT FROM AUTHOR]

Technology scaling results in that, single event effects, such as single event double-upset due to double-node charge sharing, and single event transient (i.e. an invalid pulse) propagated from upstream combinational blocks, are becoming increasingly serious with technology evolution. In this paper, a single event double-upset fully immune and single event transient filterable latch is proposed in 65 nm CMOS technology. By means of a triple-input Muller C-element, which is driven through a clock gating based triple path DICE, all internal nodes and output node of the latch not only self-recover from single event upset regardless of the energy of a striking particle, but also tolerate single event double-upset when any arbitrary combination of the node pairs is affected. Further, taking advantage of a keeper connected to the output node, the latch is insensitive to a high impedance state. Besides, making use of an embedded Schmitt trigger inverter on the propagation path, the latch also effectively filters single event transient. Simulation results have demonstrated the single event double-upset fully immunity, single event transient filterability, and cost effectiveness, i.e. approximate 60.41% area-power-delay product saving for the latch, compared with the single event double-upset fully immune DNCS-SEI latch, which cannot filter single event transient at all. [ABSTRACT FROM AUTHOR]

This paper presents a single event upset (SEU) resilient, single event transient (SET) filterable and cost effective latch (referred to as RFEL) using 45 nm CMOS commercial technology. By means of triple mutual feedback CMOS structures, one of which is an input-split Schmitt trigger, and two of which are Muller C-elements, the internal nodes and output node of the latch are self-recoverable from single event upset regardless of the energy of a striking particle. The latch filters a much wider spectrum of single event transient on account of hysteresis property of the embedded input-split Schmitt trigger, and temporal redundancy in the grouped inputs of the Muller C-element at output stage. The latch performs with lower overheads regarding area, power, and delay than most of the single event upset and single event transient simultaneously tolerated latches as well. Simulation results show that the area-power-delay-pulse product of the latch is 65.58% saving on average, and Monte Carlo simulation results demonstrate the equivalent or even less sensitivity of the latch to process, and temperature variations, compared with the previous radiation hardened latches. [ABSTRACT FROM AUTHOR]

Highlights: [•] A hydraulic model was developed to simulate a new district heating system. [•] The model is applied to such a real DH network and compared with the measurement. [•] Two operation cases were investigated to compare to the conventional DH system. [•] The new system has significant advantages on saving pumping electricity. [ABSTRACT FROM AUTHOR]

This paper presents a dual-modular-redundancy and dual-level error-interception based triple-node-upset (TNU) tolerant latch design (namely DDETT) for safety-critical applications. The DDETT latch comprises two parallel single-node-upset self-recoverable cells to store values and three C-elements to intercept errors. Both of the two cells are constructed from triple mutually-feeding-back 2-input C-elements, and the cells feed two internal C-elements for first-level error-interception. Moreover, the two internal C-elements feed an output-stage C-element for second-level error-interception, making the DDETT latch TNU-tolerant in that it can tolerate any possible TNU. This paper further presents a low-cost version of the DDETT latch, namely LCDDETT. The LCDDETT latch uses two dual-interlocked-storage-cells (DICEs) to store values and uses dual-level error-interception to tolerate any possible TNU with cost-effectiveness. Simulation results not only confirm the TNU-tolerance of the proposed latches but also demonstrate that the delay-power-area products of the DDETT and LCDDETT latches are reduced by approximately 34% and 58%, respectively. [ABSTRACT FROM AUTHOR]

Technology scaling of integrated circuits into nanoscale feature sizes has decreased the effectiveness of existing single-node-upset and double-node-upset hardening techniques in harsh radiation environments. This paper proposes a low-power triple-node-upset resilient latch (LP-TNU) based on approximate C-elements and cross-interlocking structure. The proposed LP-TNU achieves TNU resilience based on the filtering feature of C-elements and redundant feedback structure. Extensive simulation results demonstrate the robustness of the proposed latch. The proposed LP-TNU achieves extremely low power consumption because of the clock-gating technique and fewer transistors. Compared with reference latches, the proposed latch is the most robust with the lowest power consumption and power-delay-product. In addition, compared with TNU-resilient latches such as DNUHL, LCTNURL, TNURL, HLTNURL and TNUSH, the proposed LP-TNU achieves a 62.68 % reduction on average in power consumption, 9.54 % reduction on average in delay, 20.75 % reduction on average in area overhead, 69.98 % reduction on average in the area-power-delay product. At the same time, the proposed latch is insensitive to variations of the process, supply voltage, and working temperature. • With technology scaling, integrated circuits in harsh radiation environments are more vulnerable to multiple-node-upset such as double-node-upset and triple-node-upset. • This paper proposes a low-power triple-node-upset resilient latch (LP-TNU) based on approximate C-elements and cross-interlocking structure. • Compared with reference latches, the proposed latch possesses both good robustness and lower powerconsumption, and is less sensitive to PVT variations. [ABSTRACT FROM AUTHOR]

With the scaling of CMOS feature size, the multi-node upset caused by radiation has become an important reliability issue of storage devices. In order to improve the robustness of the storage devices, this paper proposes a High-Speed Quadruple-Node-Upset tolerant latch (HS-QNU). The proposed HS-QNU latch consists of two single-node-upset-resilient RFCs, two single-node-upset-resilient DICEs and a clocked quadruple-input C-element. Based on the single-node-upset-resilient ability of DICE and RFC and the blocking ability of C-element, the proposed HS-QNU latch can effectively tolerate soft errors when any four internal nodes upset by transient faults at the same time. Meanwhile, the latch effectively reduces delay and power consumption by using high-speed path and clock-gating technique. Extensive SPICE simulation in 22 nm CMOS technology shows that compared with QNUTL, the proposed latch reduces delay by 30.68 %, reduces power consumption by 30.86 %, reduces power-delay-product by 52.07 %, reduces area-power-delay-product by 49.08 %, and only increases area overhead by 6.25 %. The proposed HS-QNU latch achieves good tradeoff among delay, power consumption and area. Compared with the previous hardened latches, the proposed HS-QNU latch has the best hardening ability, the highest speed and the smallest power-delay-product. The variation analysis shows that the proposed HS-QNU latch is insensitive to temperature and voltage variations. • The size of CMOS technology continues to scale affecting the reliability of storage devices. • A high-speed quadruple-node-upset hardened latch can effectively tolerate soft errors. • The variation analysis shows the proposed latch is insensitive to temperature and voltage variations. • The proposed latch can effectively reduce delay by using high-speed path. [ABSTRACT FROM AUTHOR]