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Abstract: PBTI degradation on FinFETs with HfO2/TiN gate stack (EOT<1nm) is studied. Thinner TiN layer decreases interfacial oxide thickness, and reduces PBTI lifetime. This behavior is consistent with the results in planar devices. Corner rounding effect on PBTI is also analyzed. Finally, charge pumping measurements on devices with several fin widths devices apparently show a higher density of defects in the top-wall high-κ oxide than in the sidewall of the fin. This could explain more severe PBTI degradation. [Copyright &y& Elsevier]

Highlights: [•] Symmetric Doped Double-Gate Model (SDDGM) is applied to bulk FinFETs. [•] This model describes the transistor behavior for N-type and P-type devices. [•] This model describes the transistor behavior in all operating regions. [•] Bulk FinFETs are modeled at temperatures from 25 to 175°C. [•] Only nine parameters are used. [ABSTRACT FROM AUTHOR]

Abstract: This work presents a process to fabricate Bulk FinFETs with advancements in critical fabrication steps such as the shallow trench oxide recess and the adjustment of the fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and Bulk FinFETs on the same wafer. Morphological and electrical results indicate perfectly filled trenches, a better fin height control and a Bulk FinFET static performance similar to planar CMOS. The 20nm wide fins are fabricated using 193nm illumination lithography followed by a series of trimming steps during the trench etching, the filling and a fin re-oxidation during the steam densification of the trench filling oxide. Trench depth is 300nm and the electrically active fin height is 40nm. [Copyright &y& Elsevier]