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An output-capacitorless low-dropout regulator (LDO) based on an evolved versions of flipped voltage follower (FVF) has been proposed and simulated in a commercial 0.18 µm CMOS process in this paper. To get over the tradeoff between power consumption against other important design parameters such as loop stability and fast response, the proposed LDO is based on FVF with a push-pull stage and adopts adaptive power transistors technique, which transforms the regulator between two-stage and three-stage amplifier for different load currents. Based on such topology, more measurements are utilized to further reduce transient overshoot and improve load regulation. Simulation results verify that the recovery time is as short as 1.3 μs and the maximum undershoot and overshoot are as low as 39 mV and 42 mV, respectively. In addition, due to the adaptive power transistors technique, the quiescent current is only 16.6 μA when the load current is light. Besides, excellent load regulation is obtained as 2.7 μV/mA. [ABSTRACT FROM AUTHOR]

A type of pseudo-V 2 control, with on-chip adaptive compensation to achieve fast transient (FT) response for current mode DC–DC buck converter, has been proposed and simulated using 0.18 μm CMOS technology in this paper. Based on a new on-chip capacitor multiplier, adaptive compensation is achieved by making the compensation capacitance to track the load current. The proposed pseudo-V 2 control utilizes the output ripple to determine the duty cycle during load transient. Thus the overshoot/undershoot voltage and the transient recovery time are effectively reduced. Simulation results demonstrate the transient ripple is smaller than 50 mV and the transient recovery time is shorter than 10 μs for a 450 mA load current step. The maximum power conversion efficiency is 94.6% at 1 MHz switching frequency when input and output voltages are 5 V and 1.8 V, respectively. [ABSTRACT FROM AUTHOR]

Abstract: A low power output-capacitor-free low-dropout (LDO) regulator, with subthreshold slew-rate enhancement technique, has been proposed and simulated using a standard 0.18μm CMOS process in this paper. By utilizing such a technique, proposed LDO is able to achieve a fast transient response. Simulation results verify that the recovery time is as short as 7μs and the maximum undershoot and overshoot are as low as 55mV and 30mV, respectively. In addition, the slew-rate enhancement circuit works in the subthreshold region at steady state, and proposed LDO consumes a 46.4-μA quiescent current to provide a maximum 100-mA load with a minimum 0.2-V dropout voltage. Besides, excellent line and load regulations are obtained and the values are 0.37mV/V and 2μV/mA, respectively. [Copyright &y& Elsevier]

A CMOS voltage reference, based on body bias technique, has been proposed and simulated using SMIC 0.18μm CMOS technology in this paper. The proposed circuit can achieve a temperature coefficient of 19.4ppm/°C in a temperature range from −20°C to 80°C, and a line sensitivity of 0.024mV/V in a supply voltage range from 0.85V to 2.5V, without the use of resistors and any other special devices such as thick gate oxides MOSFETs with higher threshold voltage. The supply current at the maximum supply voltage and at 27°C is 214nA. The power supply rejection ratio without any filtering capacitor at 10Hz and 10kHz are −88.2dB and −36dB, respectively. [ABSTRACT FROM AUTHOR]

This paper presents an ultra-low-power CMOS voltage reference based on the 0.18 μ m standard CMOS technology. A temperature coefficient (TC) of 3.9 ppm/○ C without resistors or special devices is obtained by utilizing both the MOS transistor working in the deep triode region and the body bias technique. The current consumption in the minimum supply voltage of 0.85 V is as low as 96 nA. The line sensibility (LS) is 31.5 ppm/V when the supply voltage varies form 0.85 V to 3 V while the power supply rejection ration (PSRR) are −86.6 dB at 1 Hz and −50.2 dB at 100 Hz. [ABSTRACT FROM AUTHOR]