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Abstract: In this paper CMOS logic circuit performance of dopant-segregated Schottky barrier (DSSB) SOI and δ-doped partially insulated DSSB SOI (DSSB Pi-OX-δ) MOSFETs has been explored by extensive mixed-mode device/circuit simulations. It has been found that, the presence of partial buried oxide and δ-doping in an n-channel and p-channel DSSB Pi-OX-δ MOSFETs not only suppresses the off-state leakage, short-channel effects, self-heating effect and the process induced threshold voltage variability but also improves the on-state drive current of the devices. Further, although switching energy in the CMOS inverter, NAND and NOR gates based on DSSB SOI and DSSB Pi-OX-δ MOSFETs is almost equal, static power dissipation and propagation delay in the logic gates based on DSSB Pi-OX-δ MOSFET are reduced by ∼75% and ∼20% respectively over the logic gates based on DSSB SOI device. Thus, employing partial buried oxide and δ-doping under the channel of DSSB SOI MOSFET not only eliminates the potential weaknesses of this device but also makes it a suitable candidate for nanoscale CMOS logic circuits. [Copyright &y& Elsevier]

Abstract: In this paper it has been shown that employing an underlap channel created by varying the lateral doping straggle in dopant-segregated Schottky barrier SOI MOSFET not only improves the scalability but also suppresses the self-heating effect of this device. Although in strong inversion region the reduced effective gate voltage due to voltage drop across the underlap lengths reduces the drive current, in weak/moderate inversion region defined at I D =5μA/μm and V DS=0.5V the analog figures of merit such as transconductance, transconductance generation factor and intrinsic gain of the proposed underlap device are improved by 15%, 35% and 20%, respectively over the conventional overlap channel structure. In addition to this, at V DD=0.5V the gain-bandwidth product in a common-source amplifier based on proposed underlap device is improved by ∼20% over an amplifier based on the conventional overlap channel device. The mixed-mode device/circuit simulation results of CMOS inverter, NAND and the NOR gates based on these devices also show that at V DD=0.5V the switching energy, static power dissipation and the propagation delay in the case of proposed underlap device are reduced by ∼10%, ∼35% and ∼25%, respectively, over the conventional overlap device. Thus, significant improvement in analog figures of merit and the reduction in digital design metrics at lower supply voltage show the suitability of the proposed underlap device for low-power mixed-signal circuits. [Copyright &y& Elsevier]