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Abstract: A novel “plug-and-play” ESD protection methodology for wideband RF applications is demonstrated. This methodology, referred to as T-diodes, utilizes an integrated transformer together with classical ESD protection diodes. The T-diodes act as an artificial transmission line that, when placed as a “plug-and-play” ESD protection component in front of an unprotected wideband LNA, preserves the input matching of that LNA. As a demonstrator, a wideband RF LNA in 0.18μm CMOS is protected above 4.5kV HBM ESD robustness without degrading its bandwidth. [Copyright &y& Elsevier]

Abstract: Design and implementation of ESD protection for a 5.5GHz low noise amplifier (LNA) fabricated in a 90nm RF CMOS technology is presented. An on-chip inductor, added as “plug-and-play”, is used as ESD protection for the RF pins. The consequences of design and process, as well as, the limited freedom on the ESD protection implementation for all pins to be protected are presented in detail. Enhancement in the ESD robustness using additional core-clamp diodes is proposed. [Copyright &y& Elsevier]

Metal-oxide-semiconductor (MOS) devices are affected by generation, transformation, and charging of oxide and interface defects. Despite 50 years of research, the defect structures and the generation mechanisms are not fully understood. Most light has been shed onto the charging mechanisms of pre-existing oxide defects by using the non-radiative multi-phonon theory. In this work we present how the gist of physical models for pre-existing oxide defects can be efficiently abstracted at a minimal loss of physical foundation and accuracy. Together with a semi-empirical model for the generation and transformation of defects we establish a reaction-limited framework for unified simulation of bias temperature instabilities (BTI). The applications of the framework we present here cover simulation of BTI for negative (NBTI) and positive (PBTI) gate voltages, life time extrapolation, AC stress with arbitrary signals and duty cycles, and gate stack engineering. [ABSTRACT FROM AUTHOR]

A paradigm for MOSFET instabilities is outlined based on gate oxide traps and the detailed understanding of their properties. A model with trap energy levels in the gate dielectric and their misalignment with the channel Fermi level is described, offering the most successful strategy to reduce both Positive and Negative Bias Temperature Instability (PBTI and NBTI) in a range of gate stacks. Trap temporal properties are determined by tunneling between the carrier reservoir and the trap itself, as well as thermal barriers related to atomic reconfiguration. Trap electrostatic impact depends on the gate voltage and its spatial position, randomized by variations in the channel potential. All internal properties of traps are distributed, resulting in distributions of the externally observable trap parameters, and in turn in time-dependent variability in devices and circuits. [ABSTRACT FROM AUTHOR]

As-fabricated (time-zero) variability and mean device aging are nowadays routinely considered in circuit simulations and design. Time-dependent variability (reliability-related variability) is an emerging concern that needs to be considered in circuit design as well. This phenomenon in deeply scaled devices can be best understood within the so-called defect-centric picture in terms of an ensemble of individual defects. The properties of gate oxide defects are discussed. It is further shown how in particular the electrical properties can be used to construct time-dependent variability distributions and can be propagated up to transistor-level circuits. [ABSTRACT FROM AUTHOR]

• The carrier number fluctuations mechanism dominates the 1/f noise (300K-340K). • Temperature analysis of the GR noise allowed to prove the existence of traps located in the Si film and to identify them. • Correlation between the identified traps and the related technological steps were made. Low frequency noise (LFN) studies are carried out on n-channel gate all around nanowire (GAA NW) FETs. Measurements both as a function of applied polarisation at fixed temperature and conserving the same drain current bias points as a function of temperature are performed, to investigate the predominant flicker noise fluctuation mechanism and to execute low frequency noise spectroscopy allowing to identify the active traps in the depletion area of the devices. The good correlation between the normalized drain current noise S Id / I d 2 and the transconductance to drain current ratio squared (g m /I d)2 enables to establish that the 1/ f noise is related to the carrier number fluctuations mechanisms for all investigated temperatures. The study of the generation recombination (GR) noise as a function of temperature confirms the presence of a GR component for which the characteristic frequency is independent on the applied voltage and present variation with the temperature, suggesting that they are related to active traps located in the Si film. Active traps related to hydrogen and divacancies were identified. [ABSTRACT FROM AUTHOR]

A combination of hot-carrier degradation (HCD) and self-heating (SH) was acknowledged to be the most detrimental reliability issue in ultra-scaled field-effect-transistors (FETs) with confined architectures, such as fin and nanowire (NW) FETs. Although the view on whether SH accelerates or inhibits HCD in n-channel devices is controversial, it is commonly accepted that in p-channel FETs HCD becomes more pronounced due to SH. Therefore, we develop a framework for modeling coupled HCD and SH and validate it against experimental data acquired in p-channel Si NWFETs. This framework incorporates a carrier transport solver linked to a solver for the lattice heat flow equation; the latter solver allows one to evaluate a non-uniform lattice temperature distribution in the device. Carrier energy distribution functions obtained considering coordinate-dependent lattice temperature are used to calculate the rates of the multiple- and single-carrier processes of Si H bond dissociation. In addition to perturbation of carrier transport by SH, elevated lattice temperature results in enhancement of the thermal contribution to the bond rupture rate and shortens vibrational lifetime of the Si H bond, thereby reducing the multiple-carrier process rate. All these three aspects are captured by our framework, importance of each of them is analyzed, and our approach was shown to accurately reproduce experimental data. [ABSTRACT FROM AUTHOR]

Low frequency noise studies are performed in Si/SiGe superlattice I/O n-channel FinFETs. It was observed that the experimental noise spectra may contain additionally to flicker and white noise one or several generation recombination (GR) components. The methodology to estimate the noise parameters corresponding to the 1/ f noise and each GR noise contribution was detailed. It is found that the carrier number fluctuations mechanisms prevail the 1/ f noise. The important 1/ f noise level variability observed for devices having the same geometry may be related to the remote Coulomb scattering effect through the correlation between the mobility and the 1/ f noise levels. Low frequency noise spectroscopy was performed allowing to identify traps related to divacancies, hydrogen and a possible carbon contamination in Si/SiGe fins. [ABSTRACT FROM AUTHOR]