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Abstract: An epitaxial Si grown multi-layer stack consisting of boron delta-doped layers separated by 6.4nm thick undoped films has been profiled using a Cameca IMS Wf magnetic SIMS. Using low energy oblique O2 + beam, the boron depth resolution is improved from 1.66nm/decade at 500eV down to 0.83nm/decade at 150eV. At very low impact energy O2 + bombardment induces a near full oxidation of silicon and oxygen flooding is then no more needed in the analytical chamber to get a smooth sputtering of silicon at 45° incidence angle. [Copyright &y& Elsevier]

Abstract: Field emission gun (FEG) nanoprobe scanning electron transmission microscopy (STEM) techniques coupled with energy dispersive X-ray (EDX) and electron energy loss spectroscopy (EELS) are evaluated for the detection of the n-type dopant arsenic, in silicon semiconductor devices with nanometer-scale. Optimization of the experimental procedure, data extraction and the signal-to-noise ratio versus electron dose, show that arsenic detection below 0.1% should be possible. STEM EDX and EELS spectrum profiles have been quantified and compared with secondary ion mass spectrometry (SIMS) analyses which show a good agreement. In addition, the arsenic doping level found inside large and small epitaxial devices have been compared using STEM EDX-EELS profiling. The average doping level is found to be similar but variable interface segregation has been observed. Finally, STEM EDX arsenic mapping acquired in a BiCMOS transistor cross-section shows strong heterogeneities and segregation in the epitaxially grown emitter part. [Copyright &y& Elsevier]

As semiconductor devices keep shrinking in size, the fabrication of ultra-shallow junctions (USJ) is becoming a key issue for future CMOS technologies. In this study, we propose for the first time to demonstrate and extensively characterize the capability of plasma doping (PLAD) for fabricating n-type USJ. P-type silicon wafers were used and doped by plasma using AsH3/Xe or AsF5 as precursors. We have performed a Design Of Experiment (DOE) study with AsF5 implants to model the junction characteristics (junction depth Xj, sheet resistance Rs). Through a direct comparison with standard As+ ultra-low energy implants, AsF5 and AsH3 plasma-doped wafers show a significant improvement of the junctions characteristics. By optimizing each process parameter, we clearly demonstrate the ability of PLAD to fabricate, with a conventional annealing method, the N+/P ultra-shallow junctions required for the NMOS transistors of the future 65 nm CMOS technology. [Copyright &y& Elsevier]

Heterojunction Bipolar Transistors needed for high-frequency applications require precise dopant control. In-situ doped epitaxies used during device fabrication rely on surface preparation to obtain an optimized doping profile. Defects due to imperfect cleaning relates to high emitter resistance and low-frequency noise. Base epitaxy is followed by the fabrication of thin L-shaped oxide spacers and in-situ arsenic-doped emitter epitaxy by Low Pressure Chemical Vapor Deposition. A cleaning step between spacers formation and emitter epitaxy is mandatory to remove residual contamination. Hydrofluoric acid (HF) wet cleaning, in-situ remote plasma cleaning (SiconiTM) and thermal treatments have been tested. A minimum etching budget is sought for limiting spacer consumption while adequately cleaning the interface. Time Of Flight-Secondary Ion Mass Spectroscopy (TOF-SIMS) and High-Resolution Transmission Electron Microscopy (HR-TEM) are used to characterize the interface and measure levels of arsenic, oxygen, fluorine and carbon. Emitter resistance and base-emitter breakdown voltage measurements are used to show the impact on electrical figures of merit. Siconi targeting 10 Å of thermal oxide removal followed by a thermal treatment (800 °C, 60 s) in the deposition chamber results the best process among the tested ones. [Display omitted] • Emitter-base interface cleaning is fundamental for advanced Heterojunction Bipolar Transistors. • Oxide spacers and dopant diffusion limit the possible cleaning techniques. • Ex-situ and in-situ cleaning processes have been tested. • A cleaning process combining fluorine salt gas plasma etching and thermal treatment is proposed. [ABSTRACT FROM AUTHOR]

The presence of capping materials during annealing (activation for example) can substantially impact the silicon junction profiles of Complementary Metal Oxide Semiconductor Field Effect Transistors (CMOSFET), depending on the nature of these layers. In this paper we specifically investigated the boron out-diffusion from a silicon junction into the silicon oxide in presence of a silicon oxide/silicon nitride capping bi-layer similar to the stacks used to form sidewall spacers. After 120 s anneal we observed with secondary ion mass spectrometry (SIMS) substantial boron dose loss in silicon and segregation at the silicon oxide interface related to oxide and nitride material properties, in particular to the hydrogen concentration. We then modeled the boron profiles in both silicon and oxide as a function of the hydrogen static and dynamic in the materials. The exponential-like boron diffusion profiles observed in oxide are reproduced by introducing a long hop mechanism mediated with hydrogen-related defects (HRDs). [ABSTRACT FROM AUTHOR]

Ultra thin Silicon films of Silicon-on-Insulator technology are metastable and thus cannot be submitted to high temperature treatments that may roughen or disrupt the film during the set of technological steps required for device fabrication. This paper concerns the development of an efficient low temperature cleaning process of Si and SiGe surfaces that enables a subsequent good-quality epitaxy of raised source and drain. For this purpose wet-clean, plasma-clean and several combinations of both are used. We thus propose two effective surface cleaning processes with low thermal budget optimized for FD-SOI technology. [ABSTRACT FROM AUTHOR]

Optimized epitaxial processes for the filling of deep trenches are mandatory for the fabrication of advanced devices in the microelectronic industry. The use of Selective Epitaxial Growth (SEG) in deep cavities faces multiple issues such as inhomogeneities along the growth direction or defect formation. In this work, the main objective was to develop void-free processes to fill 1:6 up to 1:16 aspect ratio trenches with monocrystalline and polycrystalline Si:P respectively, in a Reduced Pressure – Chemical Vapour Deposition (RP-CVD) reactor. Previous studies suggested the use of a SiH 2 Cl 2 (DCS) + PH 3 + HCl chemistry, with an optimization of the DCS/HCl mass-flow ratio (MFR) to conformally fill large and high aspect ratio trenches with monocrystalline Si:P (c-Si:P) while preventing overgrowth at the trench entrance and voids at the bottom. Current studies were first of all conducted on blanket wafers at T = 950 °C and P = 10 Torr, in order to choose the best strategy for varying DCS/HCl MFRs. The P+ ions concentration was quantified and two trends were highlighted depending on the PH 3 partial pressure (P(PH 3)). For P(PH 3) lower than 10-5 Torr, the dopant concentration (in the 1017 - 1018 cm-3 range) increased solely with the phosphine flow and did not depend on the HCl flow. Meanwhile, for PH 3 partial pressures higher than 10-5 Torr and thus higher doping levels (between 3x1018 and 2x1019 cm-3), the P+ ions concentration increased with the PH 3 flow and decreased as the HCl flow increased. The filling of 1:6 aspect ratio trenches by monocrystalline Si:P was then achieved thanks to a three steps process with various DCS/HCl MFRs. Characterizations showed good crystalline quality together with a steady doping level of 1.3x1018 at cm-3. Further optimizations will however be required to completely suppress voids. Meanwhile, the filling of 1:16 aspect ratio trenches or needles by poly-Si:P was successfully achieved at 10 Torr with a SiH 4 + PH 3 chemistry, provided that the deposition temperature, 750°C, was low enough to avoid the formation of large poly-Si:P grains, notably at the entrance of such cavities. • Sequential epitaxial growths to fill 1:6 and 1:16 aspect ratio trenches in Si. • 950 °C and 10 Torr to fill trenches with monocrystalline Si:P 1018–1019 at cm-3 • SiH 2 Cl 2 /HCl mass flow ratios optimization to have void-free trench filling. • Low temperatures minimize voids and grain sizes when filling trenches with poly-Si:P. • 750 °C and 10 Torr to fill, thanks to SiH 4 , 1:16 cavities with poly-Si:P 1019 at cm-3 [ABSTRACT FROM AUTHOR]