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Twenty-seven Eimeria spp. field isolates from 10 European countries were examined for sensitivity to the anticoccidial combination narasin + nicarbazin. Twenty-three of the samples were collected from farms using anticoccidial medication programs, and 4 of the samples were collected from farms using coccidiosis vaccination as the exclusive coccidiosis control method. Ninety-five percent of the isolates collected from farms using in-feed anticoccidial medication demonstrated poor sensitivity to narasin + nicarbazin. By contrast, 100% of the isolates collected from the coccidiosis vaccinated farms demonstrated good sensitivity, with a highly significant reduction in oocyst output when the isolates from the vaccinated farms were fed narasin + nicarbazin. As sensitivity of in-feed anticoccidials declines, a combination of the use of vaccine and anticoccidial strategies may be required for sustainable coccidiosis control. [ABSTRACT FROM AUTHOR]

This work describes a new computational approach for modeling the radiation-induced transient current and charge collection at circuit-level. Our methodology is based on a random-walk process that takes into account both diffusion and drift of radiation-induced minority carriers in a non-constant electric field both in space and time. The model has been successfully coupled either with an internal routine or with SPICE for circuit solving and feedback on the charge-collection process. It is illustrated here for a junction impacted by an ionizing particle and embedded in a CMOS inverter. [ABSTRACT FROM AUTHOR]

Microprocessors are widely used in space applications. ARM processors fabricated with FDSOI technologies are promising for future space programs. However, radiation-hardening approaches can greatly affect the resource overhead and performance. These hardening techniques need to be evaluated at system level to better understand their effectiveness, especially for modern CMOS technologies. In this paper, two ARM® Cortex® M0 cores, a reference core and a hardened core were implemented on the same die in a 28-nm FDSOI technology. The reference core was designed with components from the standard cell library, while the other one was implemented with hardened DICE flip-flops. Both of the cores shared the same on-chip TMR-protected SRAM. Heavy ion experiments showed that the error cross section of the core with DICE flip-flops was about 2 times smaller at LET of 40 MeV·cm2·mg−1. This suggests that the contribution from logic circuits in the microprocessor cores also need to be considered for better error reduction. • The key point of system level single event effect investigation is to evaluate the vulnerability of each kind of circuits. • The cross-section contribution of each kind of circuits in the ARM processors was tested and analysed. • The results show FFs are the most vulnerable circuit and it can achieve an improvement of 2.5-5X through hardening design. • Peripheral logic circuits also take significant part in the cross-section. [ABSTRACT FROM AUTHOR]