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Highlights: [•] We developed automatic parameter extraction techniques to extract model parameters. [•] DT and TAT gate leakage current parameters have been extracted for Trigate MOSFET. [•] The correlations between gate leakage current model parameters are studied. [•] The industry standard package IC-CAP is used to consider extraction techniques. [•] The results show good agreement with the measured data in Trigate MOSFET. [ABSTRACT FROM AUTHOR]

Abstract: The temperature dependence of the gate leakage current has been developed for Double Gate (DG) MOSFETs. This model is compared with experimental data measured in Trigate MOSFETs at various temperatures with SiON as a dielectric material and SiO2 as an interfacial layer. The gate leakage current measurements at different temperatures show two different transport mechanisms, direct tunneling (DT) gate leakage and Trap-Assisted-Tunneling (TAT) current. Our analysis based on leakage current measurements in the above threshold regime for different temperatures shows that the DT current is clearly dominant over the TAT, while the opposite happens below threshold. Our model is able to explain the gate tunneling current in terms of gate voltage for different temperatures. The results of the DT current in the strong inversion regime and TAT in the subthreshold regime show good agreement with temperature dependent measurements. [Copyright &y& Elsevier]

Abstract: This paper presents a compact gate leakage current partitioning model for nanoscale Double Gate (DG) MOSFETs, using analytical models of the direct tunneling gate leakage current. Gate leakage current becomes important and an essential aspect of MOSFET modeling as the gate oxide thickness is scaled down to 1nm and below in advanced CMOS processes. We considered an ideal interface (ideal case without an interfacial layer) and two layers high k dielectric materials as gate insulators. In the case of two layers, a thin layer of SiO2 as an interfacial layer is considered. The results of the gate current partitioning components into drain and source show good agreement with 2D TCAD numerical device simulation (Silvaco Atlas). [Copyright &y& Elsevier]

Abstract: In this paper, the gate leakage current in metal-oxide-semiconductor (MOS) junctions/devices/or transistors is modeled and studied in order to find promising materials for double-gate (DG) MOSFETs at 22nm node by considering analytical models of the direct tunneling current (based on a proper calculation of the WKB tunneling probability in the gate oxide). We present a theoretical study to find the most promising gate oxide materials for the 22nm technological node with the predicted maximum value of leakage current (10−2 A/cm2) that is tolerable for that node, according to the ITRS roadmap. The effects of electron effective mass, dielectric constant k-value and barrier height on the ΔEc −k permitted values have been studied. [Copyright &y& Elsevier]

Multiple arrays of Si nanowires are required for high performance applications with high current drive requirements. Densely packed arrays are significantly affected by electrostatic screening effects deteriorating the DC and AC performance of the individual nanowire (NW). This study compares the impact of screening effects in single gate, double gate and gate all-around nanowire FETs with nanosheet FETs based on experimental data and calibrated TCAD simulation results. Moreover, evolving the NW array into nanosheet transistors turned out to yield superior performance and thus might be a candidate for future high performance electronics. We identified NW pitches of less than four times the NW diameter to be critical for the performance of an individual NW in the array with a NW performance degradation of up to 50%. However, the performance gain by having more NWs within the same area in a densely packed array overcompensates the performance drop of the individuals NWs in the array. [ABSTRACT FROM AUTHOR]

This paper presents a compact model for the DC current of Schottky barrier field-effect transistors at deep cryogenic temperatures, close to absolute zero kelvin. The proposed model is physics based and calculates the injection current over a device's Schottky barriers, by considering physical effects at these temperatures (e.g. quantum oscillations, band tail effect, phonon-assisted tunneling, etc.). For model verification, it is compared to measurements performed on nanowire Schottky barrier transistors at a temperature of 5.5 K. [ABSTRACT FROM AUTHOR]

In this paper, a physics-based DC compact model for Schottky barrier field-effect transistors at deep cryogenic temperatures is presented. The model uses simplified tunneling equations at temperatures of ϑ ≈ 0 K in order to calculate the field emission injection current at the device's Schottky barriers. Additionally, an empirical expression for including resonant tunneling effects is introduced. The compact model is also compared to and verified by measurements performed on ultra-thin body and buried oxide SOI Schottky barrier field-effect transistors and is able to capture the signature of resonant tunneling effects in the transfer characteristics. • Presents a DC compact model for Schottky barrier field-effect transistors. • Model is physics-based, closed-form and for deep cryogenic temperature environment. • Field emission current at the Schottky barrier is calculated. • Verification is done on measurements. [ABSTRACT FROM AUTHOR]