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The tunnel field-effect transistor (TFET), which utilises the band-to-band tunnelling mechanism for current conduction, provides the ability to achieve extremely low subthreshold swing (<60 mV/dec) and very low off-current, thus offering a performance advantage over conventional inversion-mode metal-oxide-semiconductor field effect transistors (MOSFETs) for the ultra-low power and ultra-low voltage operation for the next generation of transistors. In particular, the optimisation of the TFET architecture and material composition is very important because the full potential of the TFET is not yet uncovered. In this work homo- and hetero-structure nanowire TFETs, based on Si, Ge and SiGe materials, have been investigated using device simulation, for the design of source and drain doping profiles, with nanowire diameters down to 5 nm. [ABSTRACT FROM AUTHOR]

In this work, by exploiting two-dimensional (2-D) TCAD numerical simulations, we performed a study of optimum emitter coverage ratio (R opt ) to reach maximum performance on back contact-back junction (BC-BJ) solar cells. R opt exhibits a strong dependence on pitch, emitter and back surface field (BSF) doping and bulk resistivity, ranging between 0.6 and 0.95. By fixing BSF doping, emitter doping and bulk resistivity, BSF and emitter width can be optimized independently one another. The optimum BSF width and the optimum emitter width are given by a trade-off between series resistance and electrical shading losses. From the design perspective, focusing on optimizing the BSF and emitter width is more effective than optimizing R at fixed pitch or BSF width. [ABSTRACT FROM AUTHOR]

In this work, by exploiting two-dimensional (2-D) TCAD numerical simulations, we performed a study of the impact of the doping levels on the main figures of merit in the different regions of a crystalline silicon Back-Contact Back-Junction (BC-BJ) solar cell: the emitter, the Back Surface Field (BSF) and the Front Surface Field (FSF). The study is supported by a dark loss analysis which can highlight the contribution of several recombination mechanisms to the total diode saturation current. The efficiency curve as a function of doping level exhibits a bell-shape with a clearly identifiable optimum value for the three regions. The decrease in efficiency observed at lower doping values is explained in terms of higher contact recombination for BSF and emitter, and in terms of higher surface recombination for FSF. The efficiency decrease observed at higher doping values is ascribed to the higher surface recombination for FSF and Auger recombination for all cases. [ABSTRACT FROM AUTHOR]

Abstract: In order to improve the efficiency of c-Si and mc-Si solar cells, Metal Wrap Though (MWT) architecture is investigated. In this paper we implement TCAD numerical simulations to analyze the performance of MWT cells with a point busbar or a continuous busbar at the back side. The two topologies of MWT cells are compared in both illuminated and dark conditions, aiming at understanding and comparing the resistive and recombination losses. The impact of the separation region is also studied, highlighting the degradation effect on the Fill Factor (FF) and on the efficiency in the two structures. We observe that the separation region dimension leads to a higher degradation of efficiency in case of continuous busbar. [Copyright &y& Elsevier]

• STT-MRAMs based on double-barrier MTJ (DMTJ) operating at liquid nitrogen boiling point (77 K). • Reliable, energy-efficient, and high-density STT-MRAMs operating at 77 K. • DMTJ devices with relaxed retention time allow improved energy and performance at 77 K. • Energy efficiency (> 35%) under write/read accesses is achieved in contrast to 6T-SRAM. This paper investigates the impact of thermal stability relaxation in double-barrier magnetic tunnel junctions (DMTJs) for energy-efficient spin-transfer torque magnetic random access memories (STT-MRAMs) operating at the liquid nitrogen boiling point (77 K). Our study is carried out through a macrospin-based Verilog-A compact model of DMTJ, along with a 65 nm commercial process design kit (PDK) calibrated down to 77 K under silicon measurements. Comprehensive bitcell-level electrical characterization is used to estimate the energy/latency per operation and leakage power at the memory architecture-level. As a main result of our analysis, we show that energy-efficient small-to-large embedded memories can be obtained by significantly relaxing the non-volatility requirement of DMTJ devices at room temperature (i.e., by reducing the cross-section area), while maintaining the typical 10-years retention time at cryogenic temperatures. This makes DMTJ-based STT-MRAM operating at 77 K more energy-efficient than six-transistors static random-access memory (6T-SRAM) under both read and write accesses (−56% and −37% on average, respectively). Obtained results thus prove that DMTJ-based STT-MRAM with relaxed retention time is a promising alternative for the realization of reliable and energy-efficient embedded memories operating at cryogenic temperatures. [ABSTRACT FROM AUTHOR]

• STT-MRAMs based on double-barrier MTJ (DMTJ) operating at cryogenic temperatures (77 K). • DMTJs with reduced thermal stability that ensure stable states at 77 K. • DMTJ devices with relaxed non-volatility allow improved energy and performance at 77 K. • Energy efficiency (>35%) under write/read accesses is achieved in contrast to 6T-SRAM. Spin-transfer torque magnetic random-access memory (STT-MRAM) is considered as a premiere candidate for replacing conventional six-transistors static random-access memory (6T-SRAM) in processor caches. This paper explores STT-MRAMs based on double-barrier magnetic tunnel junction with two reference layers (DMTJ), while operating at cryogenic temperatures (77 K). To deal with large dynamc energy and long latency of write operation, we suggest to significantly relax the non-volatility requirement of DMTJ devices at room temperature by reducing the cross-section area, while maintaining the typical 10-years retention time at the target operating temperature. This leads the cryogenic DMTJ-based STT-MRAM to be more energy-efficient than its 6T-SRAM counterpart under both read and write operations, while exhibiting smaller area footprint. [ABSTRACT FROM AUTHOR]

This work focuses on the positive bias temperature instability of SiC-based MOSFETs under different stress voltages and temperatures. Stress experiments demonstrate that the threshold voltage shift (∆ V th) does not follow a conventional power law for long stress time, but exhibits a saturating log- time dependence attributed to the charge trapping in the pre-existing defects at the SiC/SiO 2 interface or in the SiO 2 layer. The maximum V th shift (∆ V max), which is a function of the total trap density, increases with the stress voltage (V stress) and decreases for temperatures higher than 50 °C. The time constant of the traps (τ 0) also shows an uptrend with V stress with a maximum value of around 50 °C. Moreover, the trap energy distribution (γ) slightly increases with temperature. The recovery analysis shows that an empiric universal relaxation function well describes the data with a dispersion parameter (β) that follows the Arrhenius law. Finally, the V th recovery, after the same V stress , is enhanced with temperature and also depicts a linear behavior on the Arrhenius plot. This indicates that the charge de-trapping process is thermally activated and explains the low degradation observed at high temperatures during the stress phase. • Recoverable threshold voltage degradation under different stress conditions. • The threshold voltage shift shows a saturating log-time dependence attributed to charge trapping in the pre-existing defects. • The charge de-trapping is thermally activated and explains the low degradation at high temperatures during the stress phase. • An empiric universal relaxation function well describes the recovery data. [ABSTRACT FROM AUTHOR]

This work presents a systematic analysis of the transport mechanism and surface passivation of tunneling oxide (SiO 2)/p-type poly-silicon (poly-Si(p)) junctions applied to p-type crystalline silicon (c-Si) solar cells by means of TCAD numerical simulations. We report on the impact of the buried doped region (BDR) in the c-Si wafer on the transport and passivation of SiO 2 /poly-Si(p) junctions. We show that a BDR is not necessary for carrier selective contacts (CSCs) with a tunnel oxide thinner than 1.2 nm and for surface recombination velocity at SiO 2 /c-Si interface below 1·103 cm/s. Then, we explore alternative semiconductors to poly-Si for tunnel oxide passivating contacts. We find that 3C–SiC(p) is a promising candidate thanks to its valence band offset with respect to silicon, driving the wafer surface into a condition of strong accumulation. We show that excellent SiO 2 /3C–SiC(p) junctions are obtained for doping density of the 3C–SiC(p) larger than 5·1019 cm−3 and for SiO 2 thinner than <1.2 nm. Finally, with the aim of deriving guidelines for material selection, we present an investigation on the influence of the electron affinity and bandgap of the semiconductor layer forming the passivating contact, demonstrating that conversion efficiency is maximized for built-in voltages between 0.4 and 2.6 eV. • Transport mechanisms for hole carrier selective contacts based on tunnelling oxide poly-silicon alloys. • The role of buried dopants (boron) inside c-Si wafer in terms of passivation and transport. • Alternative semiconductor materials for hole selective contacts: advantages of silicon carbide. • Electronic properties of the p-type semiconductor layer forming the passivating contact to maximize efficiency. [ABSTRACT FROM AUTHOR]

This work presents a detailed analysis of the impact of a rear point-contact (PC) scheme and a selective emitter (SE) design on the performance of a crystalline silicon ( c -Si) back contact-back junction (BC-BJ) solar cell featuring narrower highly-doped back surface field (BSF) areas and wider lowly-doped emitter areas. The analysis was performed both through light and dark J-V simulations by using a rigorous full three-dimensional (3D) electro-optical modeling approach to accurately include the 3D effects of several competing physical mechanisms occurring in a PC structure. Simulation results show that the adoption of a relatively thick and wide metallization contacting the silicon at the rear side only via small circular-shaped holes gives an efficiency improvement above 0.3% abs with respect to a conventional BC-BJ solar cell featuring a linear-contact (LC) metallization scheme. Moreover, the introduction of an optimized SE design, featuring a local deeper highly-doped (HDOP) profile underneath rear point contacts and a narrower lowly-doped (LDOP) profile at the non-contacted rear interfaces, can lead to a further efficiency enhancement of about 0.2% abs , which increases with the emitter width. [ABSTRACT FROM AUTHOR]

• Two-dimensional (2D) materials as emerging technology for next-generation electronics. • MoS 2 -based field-effect transistors (FETs) on paper substrate for flexible electronics. • Look-up-table (LUT) based Verilog-A model calibrated on measurements of fabricated devices. • Circuit simulations of cryptographic primitives such as physically unclonable functions (PUFs) • Potential of paper-based MoS 2 FETs as building blocks for hardware security applications. Two-dimensional (2D) materials are recognized as a promising beyond-CMOS technology thanks to their attractive electrical and mechanical properties, which make them particularly suitable for flexible electronics. This work investigates molybdenum disulfide (MoS 2) based field-effect transistors (FETs) fabricated on paper substrate to design hardware-security primitives such as Physically Unclonable Functions (PUFs). Circuit simulations have been performed by using a look-up-table (LUT) based Verilog-A model calibrated on electrical measurements of fabricated devices. Obtained results prove the potential of paper-based MoS 2 FETs as building blocks for next-generation flexible electronics in the field of hardware security. [ABSTRACT FROM AUTHOR]

• Smart material implication (SIMPLY) logic based on nanoscale STT-MTJs. • Managing tradeoff between error rate and energy consumption. • Tracking the temperature dependence of STT-MTJ properties to mitigate reliability degradation. Smart material implication (SIMPLY) logic has been recently proposed for the design of energy-efficient Logic-in-Memory (LIM) architectures based on non-volatile resistive memory devices. The SIMPLY logic is enabled by adding a comparator to the conventional IMPLY scheme. This allows performing a preliminary READ operation and hence the SET operation only in the case it is actually required. This work explores the SIMPLY logic scheme using nanoscale spin-transfer torque magnetic tunnel junction (STT-MTJ) devices. The performance of the STT-MTJ based SIMPLY architecture is analyzed by varying the load resistor and applied voltages to implement both READ and SET operations, while also investigating the effect of temperature on circuit operation. Obtained results show an existing tradeoff between error rate and energy consumption, which can be effectively managed by properly setting the values of load resistor and applied voltages. In addition, our analysis proves that tracking the temperature dependence of the MTJ properties through a proportional to absolute temperature (PTAT) reference voltage at the input of the comparator is beneficial to mitigate the reliability degradation under temperature variations. [ABSTRACT FROM AUTHOR]

Two-dimensional (2D) materials represent an emerging technology for transistor electronics in view of their attractive electrical and mechanical properties. This work investigates molybdenum disulfide (MoS 2) based field-effect transistors (FETs) fabricated on paper substrate for designing both digital and analog circuits, such as inverter, current mirror, and Physical Unclonable Function (PUF) bitcell. Electrical measurements of fabricated devices are exploited to setup a look-up-table (LUT)-based Verilog-A model to be integrated in a commercial circuit simulator. Obtained results prove the potential of paper-based MoS 2 FETs as building blocks of next-generation integrated circuits for a wide range of practical applications. [ABSTRACT FROM AUTHOR]

• Spin-transfer torque magnetic tunnel junction (STT-MTJ) for logic-in-memory (LIM) • Smart material implication (SIMPLY) LIM scheme based on nanoscale STT-MTJs. • More energy-efficient and reliable operation with SIMPLY against conventional IMPLY. Spin-transfer torque magnetic tunnel junction (STT-MTJ) technology is an attractive solution for designing non-volatile Logic-in-Memory (LIM) architectures. This work explores a smart material implication (SIMPLY) LIM scheme based on nanoscale STT-MTJs. The SIMPLY architecture is benchmarked against the conventional material implication (IMPLY) logic. Obtained results prove that for similar performance the STT-MTJ based SIMPLY scheme ensures more reliable operation (i.e., lower error rate by more than three orders of magnitude) and an energy saving of −70% than its IMPLY counterpart, at the only cost of minimal area overhead. [ABSTRACT FROM AUTHOR]