Search

Abstract: The carrier conduction and the degradation mechanism in n+gate p-channel metal-insulator-semiconductor field-effect-transistors with HfAlO X (Hf: 60at.%, Al: 40at.%)/SiO2 dielectric layers have been investigated using carrier separation method. Since gate current depends on substrate bias and both electron and hole currents are independent of temperature over the range of 25–150°C, the conduction mechanism for both currents is controlled by a tunneling process. As the interfacial SiO2 layer (IL) thickness increases in a fixed high-k layer thickness (T high-k), a dominant carrier in the leakage current changes from hole to electron around 2.2-nm-thick IL. This is due to an asymmetric barrier height for electrons and holes at the SiO2/Si interface. On the contrary, in the case of a fixed IL thickness of 1.3nm, the hole current is dominant in the leakage current, regardless of T high-k. It is shown that the dominant carrier in the leakage current depends on the structure of the high-k stack. Both electron and hole currents for the stress-induced-leakage-current (SILC) state increase slightly relative to the initial currents, which means that the trap generation in the high-k stack occurs near both the conduction band edge of n+poly-Si gate and the valence band edge of Si substrate. The electron current at soft breakdown (SBD) state dramatically increases over that for the SILC state, while the hole currents for both the SILC state and SBD are almost the same. This indicates that the defect sites generated in the high-k stack after SBD are located at energies near the conduction band edge of n+poly-Si gate. Both the defect generation rate and the defect size in the HfAlO X /SiO2 stacks are large compared with those in SiO2. It is inferred that, in high-k dielectric stack, the defect generation mainly occurs in the high-k side rather than the IL side, and the defect size larger than the case of SiO2 could be related to a larger dielectric constant of the high-k layer. [Copyright &y& Elsevier]