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A methodology is proposed to emulate and assess the single event effect in configuration memory on 16 nm Ultrascale+ MPSoC. The solution depends on fault injection and fault tree analysis. Three image processing applications, including histogram computation, image stretch and sobel edge detection, are used as the benchmarks. The results demonstrate 38.1% to 40.5% system errors cannot be recovered, although the SEM sub-system is adopted to recover the corresponding upset in the configuration memory.

Commercial SRAM-based FPGAs are widely used in aerospace applications thanks to their limited costs and high performances. Dynamic Partial Reconfigurability (DPR) allows to rewrite sections of the configuration memory of these devices while they are normally working. This is a powerful feature which provides advantages in terms of area, power consumption and flexibility. Moreover, DPR plays the main role in the recovery from faults that may occur in the configuration memory of the device when it operates in a radiation environment. Indeed, ionized particles which strike electronic devices, may cause various types of events. The Single Event Transient (SET) is a well-known phenomenon, which affects sensitive nodes causing transitory voltage spikes that can be sampled by a memory element, causing a fault. In this paper, an evaluation methodology for the errors caused by SETs during the reconfiguration of the configuration memory in SRAM-based FPGAs is presented. The evaluation methodology includes the fault model evaluation and the development of a fault injection and error evaluation workflow. The illustrated methodology has been applied on a physical device implementing a benchmark design and the obtained results are reported.

Flash-based Field Programmable Gate Array (FPGA) devices are nowadays golden core of many applications especially in space and avionic fields where reliability is an important concern. In particular, for Flash-based FPGAs, when adopted in those applications, the main concern is radiation-induced voltage glitches known as Single Event Transient (SET) in the combinational logic. In this work, a new CAD tool is presented for evaluating the sensitivity of the implemented circuit regarding SET and mitigating this effect. This tool has been applied to EUCLID space mission project including more than ten modules. The experimental results demonstrate the efficiency of the proposed tool.

General Purpose Graphics Processing Units (GPGPUs) are increasingly adopted thanks to their high computational capabilities. GPGPUs are preferable to CPUs for a large range of computationally intensive applications, not necessarily related to computer graphics. Within the high performance computing context, GPGPUs must require a large amount of resources and have plenty execution units. GPGPUs are becoming attractive for safety-critical applications where the phenomenon of transient errors is a major concern. In this paper we propose a novel transient error fault injection simulation methodology for the accurate simulation of GPGPUs applications during the occurrence of transient errors. The developed environment allows to inject transient errors within all the memory area of GPGPUs and into not user-accessible resources such as in streaming processors combinational logic and sequential elements. The capability of the fault injection simulation platform has been evaluated testing three benchmark applications including mitigation approaches such as Duplication With Comparison, Triple Modular Redundancy and Algorithm Based Fault Tolerance. The amount of computational costs and time measured is minimal thus enabling the usage of the developed approach for effective transient errors evaluation.

The present work proposes a methodology to predict radiation-induced Single Event Transient (SET) phenomena within the silicon structure of Flash-based FPGA devices. The method is based on a MonteCarlo analysis, which allows to calculate the effective duration and amplitude of the SET once generated by the radiation strike. The method allows to effectively characterize the sensitivity of a circuit against the transient effect phenomenon. Experimental results provide a comparison between different radiation tests data, performed with different Linear Energy Transfer (LET) and the respective sensitiveness of SETs.

The increasing technology node scaling makes VLSI devices extremely vulnerable to Single Event Effects (SEEs) induced by highly charged particles such as heavy ions, increasing the sensitivity to Single Event Transients (SETs). In this paper, we describe a new methodology combining an analytical and oriented model for analyzing the sensitivity of SET nanometric technologies. The paper includes radiation test experiments performed on Flash-based FPGAs using heavy ions radiation beam. Experimental results are detailed and commented demonstrating the effective mitigation capabilities thanks to the adoption of the developed model.