1. A Low Power Parallel Sequential Decoder for Convolutional Codes
- Author
-
Adil El Bourichi
- Subjects
Computer Networks and Communications ,Computer science ,Data_CODINGANDINFORMATIONTHEORY ,Sequential decoding ,Serial concatenated convolutional codes ,Viterbi algorithm ,Computer Graphics and Computer-Aided Design ,Human-Computer Interaction ,Computer Science::Hardware Architecture ,symbols.namesake ,Soft-decision decoder ,Viterbi decoder ,Artificial Intelligence ,Convolutional code ,Management of Technology and Innovation ,symbols ,Bit error rate ,Electronic engineering ,Algorithm ,Decoding methods ,Computer Science::Information Theory ,Information Systems - Abstract
A novel decoding algorithm having a simple hardware realization is proposed for convolutional codes. The proposed decoder accepts a simple implementation in hardware in terms of area occupancy and power consumption compared to other decoders for convolutional codes such as those based on the Viterbi algorithm (VA). Furthermore, the processing delays due to looking back and forward in a trellis as in sequential decoding algorithms are avoided, which makes the proposed decoder suitable for fast high data rates wireless communication systems. Simulation results show a comparable bit error rate (BER) performance to optimal decoders with a reduction of power consumption of 60% compared to Viterbi decoders.
- Published
- 2013