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Copyright of Computer Engineering & Science / Jisuanji Gongcheng yu Kexue is the property of Computer Engineering & Science and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

High speed serial interface is the key intellectual property (IP) for the inter-chip interconnection during the high performance computers and data centers. As the single-channel rate of the serial interface evolves from 56 Gbps to 112 Gbps, the high speed serial interface faces a sharp increase in the bit error rate (BER), which seriously affects the interconnection performance and the system stability. In order to solve the problem of the high bit error rate at 112 Gbps PAM4 receiver, a cooperative adaptive equalizer is proposed in this paper. Firstly, an adaptive cooperative equalization algorithm for three kinds of equalizers is proposed to achieve low bit error under the condition of large insertion losses. Then the blind adaptive equalization algorithm based on decision feedback equalizer is proposed to shorten the link training time and reduce the hardware overhead. This paper completes the circuit implementation of the receiver with the cooperative adaptive equalizer under the 12 nm CMOS technology. The simulation results show that the receiver with the proposed cooperative adaptive equalizer can steadily receive the 112 Gbps PAM4 signal under 36.5 dB condition with the BER less than 1e-12. It also can achieve the convergence period of about 400 ns and a power consumption increase of only about 2.3%. [ABSTRACT FROM AUTHOR]