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Since the introduction of Cu/low-k as the interconnect material, the chip-package interaction (CPI) has become a critical reliability challenge for flip chip packages. Revision of underfill material must be considered, which may compromise the life of flipchip interconnect by releasing the stresses transferred to the silicon devices from the solder bumps, and thereby maintain the overall package reliability. Thus, it is important to understand the thermo-mechanical behavior of solder bumps. In this study, the solder bump reliability in flip chip package was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermo-mechanical behavior of solder joints, especially the solder bumps located at the chip corners where most failures usually occur was investigated. Digital Image Correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of a solder bump of flip-chip package subjected to thermal loading from 25°C to 100°C. As a specimen preparation for DIC technique, a flip-chip specimen was cross-sectioned before a manual polishing process followed by wet etching method in order to generate natural speckle patterns with high enough contrast on the measuring surface. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments, and validated with experimental results. Then, using the FEA analysis, parametric study for underfill material properties were performed on the reliability of flip chip package, by varying the glass transition temperature (Tg), Young’s modulus (E), and coefficient of thermal expansion (CTE). Averaged plastic work of the corner solder bump and stress at the die side were obtained and used as damage indicators for solder bumps and low-k dielectrics layer, respectively. The results show that high Tg, and E of underfill are generally desirable to improve the reliability of solder interconnects in the flip chip package.Copyright © 2011 by ASME

Since the thickness of stacked silicon chips in 3D integration has been thinned to less than 100 μm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the local distribution of thermal residual stress appears in the stacked chips due to the periodic alignment of metallic bumps, and they sometimes deteriorate mechanical and electrical reliability of electronic products. In this paper, the dominant structural factors of the local residual stress in a silicon chip are investigated quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 μm, and an unit cell consisted of four gauges with different crystallographic directions. This alignment of the strain gauges enables us to measure the tensor component of three-dimensional stress fields separately. Test flip chip substrates were made of silicon chip on which the area-arrayed tin/copper bumps were electroplated. The width of a bump was fixed at 200 μm, and the bump pitch was varied from 400 μm to 1000 μm. The thickness of the copper bump was about 40 μm and that of tin layer was about 10 μm. This tin layer was used for the formation of rigid joint by alloying it with copper interconnection formed on a stress sensing chip. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa depending on the combination of materials such as bump, underfill, and interconnections. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps. It was also confirmed that not only the control of mechanical properties of electroplated copper thin films, but also the hound’s-tooth alignment of a through silicon via and a bump are indispensable for minimizing the packaging-induced stress in the three-dimensionally mounted chips. This test chip is very effective for evaluating the packaging-process-induced stress in 3D stacked chips quantitatively.

Flip chip package is widely used in the electronic device manufacturing industry. The top side of a flip chip device is manufactured with solder bumps. The device is then flipped on its top so that the solder bumps can be bonded to a substrate, forming the mechanical and electrical connection between the device and substrate. As a result, the solder bumps are sandwiched between the silicon die and the substrate, making them no longer visible for usual inspection. A novel solder joint inspection system capable of evaluating the quality of the hidden solder bumps on a flip chip package has been developed using laser ultrasound techniques. The system pulses a laser onto the top surface of a chip package to generate ultrasonic waves in the package and excite structural vibrations which can then be measured using an interferometer. Since defective solder bumps cause changes in the transient vibration response of a tested sample, quality of the tested sample can be assessed by correlating its vibration responses to that of a known good device. A limitation of this implementation is the necessity of a known-good reference chip package, which typically involves expensive testing using alternate methods. In this paper, the development of a method capable of generating a virtual reference chip package is presented. This method, called Hybrid Reference Method, uses a statistical approach to find which packages in a sample set are most similar and then averages their time domain signals to generate a virtual chip package, known as the Hybrid Reference Package. The signals associated with Hybrid Reference Package are then correlated with the time domain signals obtained from the packages under inspection to obtain a quality signature. Finally, defective and non-defective chip packages are separated by estimating a beta distribution that fits the quality signature histogram of the inspected packages and then determining a cutoff threshold for an acceptable quality signature. This method was applied to two types of flip chip packages where no pre-established known-good reference package was available. The results of this quality analysis were validated by comparison with electrical test and X-ray results.

Generally, underfill material is adopted for encapsulation of flip chip package. And, the role of the underfill materials has become important day by day due to variant requirements for higher reliability of flip chip package. Also lower warpage gives higher mount-ability of the flip chip package and the small changes in the warpage of the package during the thermal cycle mitigate the stress working at the bump/substrate interface and bump/chip interface. Therefore, controlling the warpage of the flip chip package becomes very important problem for enhancing the performance of the package, i.e., the higher mount-ability and longer interconnect life. In this study, the effect of physical properties of underfill materials and substrates on the warpage behavior and the interconnect reliability of the flip chip package is reported. It was found from the experiments that the selection of an underfill and a substrate gave the highest interconnect reliability for the bump bonds. In addition to control the warpage behavior of the package during assembly, by selecting the suitable underfill material and substrate, the flip chip package with lower warpage and higher interconnect reliability can be realized.Copyright © 2009 by ASME

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more Input/Output (I/O) and better electrical characteristics under same package form factor. Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pin accommodation and high transmission speed. However, the flip chip technology is encountering its structure limitation as the bump pitch is getting smaller and smaller because the spherical geometry bump shape is to limit the fine bump pitch arrangement and it’s also difficult to fill by underfill between narrow gaps. As this demand, a new fine bump pitch technology is developed as “Cu pillar bump” with the structure of Cu post and solder tip. The Cu pillar bump is plating process manufactured structure and composes with copper cylinder (Cu post) and mushroom shape solder cap (Solder tip). The geometry of Cu pillar bump not only provides a finer bump pitch, but also enhances the thermal performances due to the higher conductivity than conventional solder material. This paper mainly characterized the Cu pillar bump structure stress performances of FCBGA package to prevent reliability failures by finite element models. First, the bump stress and Cu/low-k stress of Cu pillar bump were studied to compare with conventional bump structure. The purpose is to investigate the potential reliability risk of Cu pillar bump structure. Secondly, the bump stress and Cu/low-k stress distribution were evaluated for different Polyimide (PI) layer, Under Bump Metallization (UBM) size and solder mask opening (SMO) size. This study can show the stress contribution of each design factor. Thirdly, a matrix which combination UBM size, Cu post thickness, SMO size, PI opening and PI thickness were studied to observe the stress distribution. Finally, the stress simulation results were experimentally validated by reliability tests.

Flip-chip technology has been introduced in recent years which accommodate the ever increasing demands for higher performance and I/O density, while achieving smaller form factor and offering a cost effective solution. As the industry moves toward the 65nm and 45nm technology node, die sizes require a significant reduction while accommodating the need for tighter and finer pitches. For decades, the C4 process has served as the main interconnect method in the flip-chip package. But with bump pitches shrinking, the solder bump based C4 process is facing challenges in terms of reducing pitch and underfill process. At the same time, increasing challenges for flip-chip are seen by the movement toward lead-free solder bumps and low-k dielectric layers. This work conducted simulations and analyses on Tessera developmental μPILR flip chip package incorporating a 130um pitch bump array, using 3-D finite element method (FEM). This study explores the effect of various design parameters on package reliability while providing suggestions for selecting packaging materials. Based on modeling data certain set of over mold, underfill and thermal interface materials enhance overall package reliability performance. Solder fatigue life prediction was performed and solder bump reliability was compared for Tessera flip chip technology and standard flip chip solder joints using Modified Anand solder material properties and Darveaux fatigue life prediction theory. Further more, fracture mechanics approach was applied, and energy release rates were obtained in order to check reliability of low-k dielectric layer, provided passive/low-k material selection. The data presented here provides a baseline for reliability/feasibility of Tessera developmental μPILR flip chip package design for 130um bump pitch. Experimental reliability data is not complete at this time but will be available and published soon.Copyright © 2008 by ASME

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

Flip chip packaging is one of the fastest growing segments in electronics packaging technology. The semiconductor packaging industry is continuing to migrate towards Pb-free electronics assembly. Therefore, the development of compatible materials for Pb-free flip chip packaging is critical to this transition [1]. Flip chip devices are commonly underfilled to compensate for the mismatch in the Coefficient of Thermal Expansion (CTE) between the die and the chip carrier. The No Flow Underfill (NFU) process is a type that can increase the throughput of the flip chip assembly process and reduce manufacturing costs. Significant research has been performed to develop NFUs for eutectic applications. However, further research is required for the development of NFUs that are compatible with the Pb-free solders and the high temperature reflow process associated with these solders. In this paper, the challenges associated with the development of 'filled' underfill formulations for assembly with the 95.5Sn/3.8Ag/0.7Cu bumped flip chip devices are discussed. The effects of process variables that affect voiding in the underfill layer have been presented. The impact on voiding due to stencil printing of the underfill has been discussed. The impact on assembly reliability due to the underfill material properties has also been reported.Copyright © 2006 by General Motors Corporation

A new nondestructive evaluation method of adhesion condition between a Si chip and small metallic bumps in a flip chip bonding structure is proposed. The local deformation of a surface of a Si chip mounted on a substrate increases drastically between two bumps with decrease of the thickness of the chip thinner than 200 μm. The magnitude of the local deformation exceeds 100 nm easily. Once the lack or delamination of the metallic bumps occurs at the interface, the local deformation at a surface of a Si chip around the bump changes remarkably. The change of the magnitude of the local deformation reaches about 50 nm to 600 nm depending on the thickness of the chip. Such a small change of deformation can be measured using a scanning blue laser microscope. Therefore, the adhesion condition of the area-arrayed bumps can be examined by measuring the local deformation of a surface of an LSI chip mounted on a substrate.Copyright © 2005 by ASME

SnAgCu solder used in laminate package like PBGA and CSP BGA to replace eutectic SnPb as interconnection has become major trend in the electronic industry. But unlike well-known failure mode of wire bonding package, flip chip package with SnAgCu inner solder bump and external solder ball as electrical interconnection present a extremely different failure mode with wire-bonding package from a point of view in material and process. In this study, one 16mm×16mm 3000 I/O SnAgCu wafer bumping using screen-printing process was explored including the effects of reflow times, high temperature storage life (HTSL) and temperature cycle test (TCT) on bump shear strength. Furthermore, the qualified wafer bumping is assembled by flip chip assembly with various underfill material and specific organic build-up substrate, then is subject to MSL4/260°C precondition and temperature cycle test to observe the underfill effect on SnAgCu bump protection and solder joint life. Various failure modes in the flip chip package like solder bump, underfill and UBM and so on, will be scrutinized with SEM. And finally, best material combination will be addressed to make the lead free flip package successful.Copyright © 2003 by ASME

Effective cooling of electronic chips is crucial for reliability and performance of electronic devices. Steadily increasing power dissipation in both devices and interconnects motivate the investigation of chip-centric thermal management as opposed to traditional package-centric solutions. In this work, we explore the fundamental limits for heat removal from a model chip for various configurations. Temperature rise when the chip is embedded in an infinite solid is computed for different thermal conductivities of the medium to pin down the best that can be achieved with conduction based thermal management. Next, a chip attached to a spreader plate with convection boundary condition on top was considered. A brief review of interface thermal resistances and partitioning of overall thermal resistance is presented for current generation microprocessors. Based upon the analysis it is concluded that far-term cooling solutions might necessitate integration with chip/interconnect-stack to meet the challenges. In addition, this would require concurrent thermal and electrical design/fabrication of future high-performance microprocessors.

Graduate Assistant, Ph.D candidate In this study, a silicon base piezoresistive pressure sensor using flip chip and flex circuit packaging technologies is studied, designed and analyzed. A novel designed pressure sensor using flip chip packaging with spacer is employed to substitute the conventional chip on board or SOP packaging technology. Subsequently, a finite element method (FEM) is adopted for the designing of the sensor performance. Thermal and pressure loading is applied on the sensor to study the system sensitivity as well as the thermal and packaging effect. The performance of novel packaging pressure sensor is compared with that of the conventional one to demonstrate the feasibility of this novel design. The findings depict that this novel packaging design can not only maintain well sensor sensitivity but also reduce the thermal and packaging effect of the pressure sensor.

This research establishes a micro-macro 3D finite element model for no underfill flip chip BGA package. The no underfill package uses a ceramic-like (CTE close to silicon) material mounted on the backside of the flip chip substrate to constrain the thermal expansion of the organic substrate and enhance the reliability of the solder joint. This work attempts to design a constrained structure to enhance the reliability of the no underfill flip chip package. For the special design of constrained structure, a full-scale 3D finite element model is needed to investigate some mechanical behaviors that cannot be revealed by the 2D finite element model. However, to establish a full-scale 3D finite element model, the large computation time is an issue. The equivalent beam concept is adopted in this research to overcome this drawback of the finite element models. The results indicate that the equivalent beam concept is a feasible methodology for reducing the computation time of the 3D finite element model. Further, the new design structure could improve package reliability, increase manufacturing throughput and thermal performance, and maintain reworkability of the flip chip structure.Copyright © 2002 by ASME