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Thermal management of very large-scale computers will have to leave the traditional well-beaten path. Up to the present time, the primary concern has been with rising heat flux on the integrated circuit chip, while a space has been available for the implementation of high-performance cooling design. In future systems, the spatial constraint will become a primary determinant of thermal management methodology. To corroborate this perspective, the evolution of computer's hardware morphology is simulated. Simulation tool is the geometric model, where the model structure is composed of circuit cells and platforms for circuit blocks. The cell is the minimum circuit element whose size is pegged to the technology node, while the total number of cells represents the system size. The platforms are the models of microprocessor chips, multichip modules (MCMs), and printed wiring boards (PWBs). The major points of discussion are as follows: (1) The system morphology is dictated by the competition between the progress of technology node and the demand for increase in the system size. (2) Only where the miniaturization of cells is achieved so as to deploy a system on a few PWBs, ample space is created for thermal management. (3) In the future, the cell miniaturization will hit the physical limit, while the demand for larger systems will be unabated. Liquid cooling, where the coolant is driven through very long microchannels, may provide a viable thermal solution.

Computational Fluid Dynamics (CFD) codes have proved their high potential as a tool of thermal design of electronic equipment. However, as the product development cycle is shortened, the CFD-based thermal design needs a new format that allows the packaging designer fast and versatile searches for better design options. The most serious factor that slows the CFD-based design is geometric complexity created by packing various components in a tight space of the system box. In a proposed methodology coined “Build-up Approach (BUA),” CFD simulations are conducted on a set of hardware models to gain insight into the effects of component placement on the junction temperature. Two algorithms are introduced before and after CFD simulations: one defines the geometric parameters through singular value decomposition (SVD) of components placement patterns and the other identifies important geometric parameters by means of the Taguchi method. A case study was conducted on a simple hardware model (benchmark model) that embodies essential features of portable electronic equipment. The results proved the effectiveness of these algorithms in measuring the relative importance of geometric parameters and weeding out unimportant geometric details.

This paper reviews the existing knowledge base about thermal contact resistance in cooling electronic equipment, and also highlights some novel issues that are emerging with the advent of compact electronic equipment. Where a high contact pressure is tolerable, such as in cooling power electronic devices, the experimental data and the theoretical models that have been developed to this day provide useful guides for the management of contact resistance. In such applications the compression load and a technique to enhance interface heat transfer need be examined, weighing their relative importance in the entire heat transfer system. Using the Yovanovich correlation for contact resistance and assuming water-cooled or air-cooled heat sinks, the contact pressure ranges of practical importance are identified. The case studies revealed that contact pressures around and less than 1–4 MPa are often sufficient to make the contact conductance comparable to the convective conductance in the water-cooled channel. The threshold pressure is much lower for the air-cooled case, around 0.2–0.6 MPa. However, heat transfer data in such intermediate pressure ranges are relatively few. For compact electronic equipment, such as laptop computers, the contact conductance to a thin heat spreader plate is becoming an issue of prime importance. In a constrained space the heat flow across the interface is affected by the heat conduction paths beyond the interface. This is illustrated using an example where warped heat sources are in contact with a heat spreader. It is shown that, with decreasing heat spreader thickness, the warping of the heat source has an increasing influence on the contact resistance.

The current study involves two-phase cooling from enhanced structures whose dimensions have been changed systematically using microfabrication techniques. The aim is to optimize the dimensions to maximize the heat transfer. The enhanced structure used in this study consists of a stacked network of interconnecting channels making it highly porous. The effect of varying the pore size, pitch and height on the boiling performance was studied, with fluorocarbon FC-72 as the working fluid. While most of the previous studies on the mechanism of enhanced nucleate boiling have focused on a small range of wall superheats (0–4 K), the present study covers a wider range (as high as 30 K). A larger pore and smaller pitch resulted in higher heat dissipation at all heat fluxes. The effect of stacking multiple layers showed a proportional increase in heat dissipation (with additional layers) in a certain range of wall superheat values only. In the wall superheat range 8–13 K, no appreciable difference was observed between a single layer structure and a three layer structure. A fin effect combined with change in the boiling phenomenon within the sub-surface layers is proposed to explain this effect.

An experimental study of forced convection in impinging flow, using fluorocarbon FX3250 and a simulated electronic chip, was performed. A test section consisting of a 35 mm long, 1 mm wide slot nozzle in a 2 mm thick plate offset 2 mm from the heat source was used. The simulated chip array consisted of five foil strip (4 mm wide) heaters, positioned with the center strip directly beneath the slot nozzle. The velocity of the coolant was varied from 0.53 to 5 m/s, and the subcooling in the range from 2 to 21 K. The experiments were conducted focusing on two cases. First, only the center strip was heated. Second, all the heaters were energized, and the strip-by-strip variations of heat transfer were measured. The critical heat flux (CHF) on the center strip, determined by sensing the onset of oscillations and subsequent rapid rise of foil temperatures, was found considerably lower than those predicted by the existing correlations. It is pointed out that the thermal mass of the test heater could be an important factor for the CHF. The heat transfer behavior of other strips showed channel-flow or jet-impingement mode depending on the strip location and the coolant flow rate. [S1043-7398(00)00202-4]

The study of optimization of finned heat sinks for impingement cooling of electronic components was undertaken. The procedure was based on a semiempirical zonal approach to the determination of thermal resistance as well as pressure drop. To test the validity of the model’s predictions, experiments and CFD (computational fluid dynamics) simulations were performed. The results provided support for the approach. The model enables cost-effective design calculations to be performed for the optimization of heat sinks. We performed such calculations to optimize an LSI heat sink in consideration of sixteen design parameters, including fin thickness, fin spacing, fin height, and flow-orifice dimensions. For the particular application considered in our study, the optimum fin thickness was found to be 0.15 mm. The characteristics and limitations of air cooling for such applications were investigated under various conditions.

Since the advent of modern electronics technology, heat transfer science and engineering has served in the development of computer technology. The computer as an object of heat transfer research has a unique aspect; it undergoes morphological transitions and diversifications in step with the progress of microelectronics technology. Evolution of computer's hardware manifests itself in increasing packing density of electronic circuits, modularization of circuit assemblies, and increasing hierarchical levels of system internal structures. These features are produced by the confluence of various factors; the primary factors are the pursuit of ever higher processing performance, less spatial occupancy, and higher energy utilization efficiency. The cost constraint on manufacturing also plays a crucial role in the evolution of computer's hardware. Besides, the drive to make computers ubiquitous parts of our society generates diverse computational devices. Concomitant developments in heat generation density and heat transfer paths pose fresh challenges to thermal management. In an introductory part of the paper, I recollect our experiences in the mainframe computers of the 1980s, where the system's morphological transition allowed the adoption of water cooling. Then, generic interpretations of the hardware evolution are attempted, which include recapturing the past experience. Projection of the evolutionary trend points to shrinking space for coolant flow, the process commonly in progress in all classes of computers today. The demand for compact packaging will rise to an extreme level in supercomputers, and present the need to refocus our research on microchannel cooling. Increasing complexity of coolant flow paths in small equipment poses a challenge to a user of computational fluid dynamics (CFD) simulation code. In highly integrated circuits the paths of electric current and heat become coupled, and coupled paths make the electrical/thermal codesign an extremely challenging task. These issues are illustrated using the examples of a consumer product, a printed circuit board (PCB), and a many-core processor chip.

Heat conduction analysis is performed on a model system to survey the effects of geometric and thermal parameters on the temperature of an embedded heat source. A box model has the geometric characteristics of hand-held devices and has a laminar organization composed of a printed circuit board (PCB), air gap, and a system casing. Exploiting the laminar organization and thinness of the laminate an approximate solution is derived. The solution is used to produce a guide for thermal design analysts, which is concerned with the sensitivity of the heat source temperature to the effective thermal conductivity of the PCB. Numerical examples are shown for the models that have typical dimensions and material properties of actual equipment and PCB.

A system of temperature calculations is developed to study the conditions leading to hot spot occurrence on multicore processor chips. The analysis is performed on a physical model which incorporates certain salient features of multicore processor. The model has active and background cells laid out in a checkered pattern, and the pattern repeats itself in fine grain active cells. The die has a buried dioxide and a wiring layer stacked on the die body, and heat sources are placed at the wiring layer/buried oxide interface. With this model we explore the effects of various parameters on the target spot temperature. The parameters are the die dimensions, the materials' thermal conductivities, the effective heat transfer coefficients on the die surfaces, the power map, and the spatial resolution with which we view the power and temperature distributions on the die. Closed-form analytical solutions are derived and used to examine the roles of these parameters in creating hot spots. The present paper reports the details of mathematical formulations and steps of temperature calculation. The results for a particular example case are included to illustrate what can be learned from the calculations.

The objective of this study is to understand the effects of various parameters involved in the chip design and cooling on the occurrence of hot spots on a multicore processor chip. The thermal environment for the die is determined by the cooling design which differs distinctly between different classes of electronic equipment. In the present study, like many other hot spot studies, the effective heat transfer coefficient represents the thermal environment for the die, but, its representative values are derived for different cooling schemes in order to examine in what classes of electronic equipment the hot spot concern grows. The cooling modes under study are high-performance air-cooling, high-performance liquid-cooling, conventional air-cooling, and oil-cooling in infrared radiation (IR) thermography setup. Temperature calculations were performed on a model which is designed to facilitate the study of several questions that have not been fully addressed in the existing literature. These questions are concerned with the granularity of power and temperature distributions, thermal interactions between circuits on the die, the roles of on-chip wiring layer and the buried dioxide in heat spreading, and the mechanism of producing temperature contrast across the die. The main results of calculations are the temperature of the target spot and the temperature contrast across the die. Temperature contrasts are predicted in a range 10–25 K, and the results indicate that a major part of the temperature contrast is formed at a granularity corresponding to the size of functional units on actual microprocessor chips. At a fine granularity level and under a scenario of high power concentration, the on-chip wiring layer and the buried oxide play some roles in heat spreading, but their impact on the temperature is generally small. However, the details of circuits need to be taken into account in future studies in order to investigate the possibility of nanometer-scale hot spots. Attention is also called to the need to understand the effect of temperature nonuniformity on the processor performance for which low temperature at inactive cells makes a major contribution. In contrast to the situation for the die under forced convection cooling, the die in passively cooled compact equipment is in distinctly different thermal environment. Strong thermal coupling between the die and the system structure necessitates the integration of package and system level analysis with the die-level analysis.

As electronic devices and equipment are finding their ways into diverse applications, their physical integrity becomes a matter of utmost concern. The thermal design criteria customarily assumed in many of previous heat transfer research programs have to be replaced by those on the thermomechanical load in compact systems. Attempts to find thermal and stress fields in critical parts of components, however, are beset by geometrical complexities and multiple length and time scales involved in transport processes in electronic equipment. Modeling of complex systems is the subject left for further rationalization. Also needed is the foresight about possible hardware morphologies taken by electronic equipment in the future. In view of possible saturation of 2D packaging technology, heat transfer studies for 3D packaging are worth being undertaken. Common to different scenarios of hardware development is the need to critically review the methodology and focuses of fundamental heat transfer research.

Conjugate heat transfer from a surface-mounted block (31 × 31 × 7 mm3) to forced convective air flow (1–7 m/s) in a parallel-plate channel was studied experimentally and analytically. Particular attention was directed to the heat flow from the block to the floor through the block support, which was eventually transferred to the air flow over the floor. The concepts of adiabatic wall temperature (Tad) and adiabatic heat transfer coefficient (had) were employed to account for the effect of thermal wake shed from the block on the heat transfer from the floor. The experimental data of Tad and had were used in setting the boundary condition for the numerical analysis of heat conduction in the floor. The accuracy of the numerical predictions of the thermal conductances for different heat flow paths was proven experimentally. The heat conduction analysis code was then used to find the heat transfer capability of various block-support/floor combinations.

An experimental study was performed to investigate the local characteristics of heat transfer from vertical simulated micro-chips to impinging submerged circular water jets. The effects of jet velocity, and nozzle-to-plate spacing were studied in the range of Re = 5.0 × 103 ˜ 3.6 × 104. Heat transfer rates at the stagnation point and local heat transfer distributions were correlated. Transition from laminar to turbulent flow was observed.

An analytical model is developed to estimate the heat transfer performance of printed circuit board (PCBs). The PCB under study is the substrate for a ball-grid-array (BGA) package. Under the BGA, the PCB has a belt of densely populated through-vias that penetrate the laminate of horizontal copper and resin; outside the BGA-covered area the board is a copper/resin laminate and its surfaces are exposed to cooling air. Calculations are performed on a sample board having the dimensions 11×11 cm2 (footprint)×1.26 mm (thickness). The model of the board has two internal layers of continuous copper (0.03 mm thick) and through-vias under a 4.4×4.4 cm2 BGA package. The impacts of board design parameters on the temperature and the heat flow are presented; the parameters are the width of the insulation gap around the via, the area of copper coverage at the via bottom, and the population of vias.

The porous surface structure was manufactured with precision for the experimental study of nucleate boiling heat transfer in R-11. Boiling curves and the data of bubble formation were obtained with a variety of geometrical and operational parameters; the pore diameters were of 50, 100, 150 μm, there was a combination of pores of different sizes; and the system pressures were of 0.04, 0.1, 0.23 MPa. The boiling curves exhibit certain trends effected by the diameter and population density of pores. A combination of high system pressure and pore sizes of 100 or 150 μm dia enables boiling to persist even when the wall superheat is reduced to an extremely low level of 0.1 K. A noteworthy feature of porous surface boiling is that intense bubble formation does not necessarily yield a high heat-transfer performance. Examination of the data indicates that liquid suction and evaporation inside the cavities are a proable mechanism of boiling with small temperature differences.

Based on the experimental results reported in Part I, an analytical model of the dynamic cycle of bubble formation is proposed. The cycle consists of a waiting period and a bubble growth period; in the former the pressure in the tunnel is increased due to evaporation from internally held meniscuses and in the latter a certain amount of pool liquid is sucked in the tunnel to be subsequently evaporated. The equations are formulated with the adoption of a moderate number of empirical constants. Their solutions give the predictions of latent heat flux due to internal evaporation, population density of active sites, and frequency of bubble formation. The population density is then used to estimate convective heat flux on the outer surface from the empirical correlation established in Part I. The analytical predictions are compared with the experimental data of Part I. The results are encouraging and indicate the course of future study to implement the model.

Enhancement of nucleate boiling heat transfer has been studied with the structured surfaces composed of interconnected internal cavities in the form of tunnels and small pores connecting the pool liquid and the tunnels. The boiling curves of R-11, water and nitrogen show 80 to 90 percent reduction of wall superheat required to transfer the same heat flux as that on plain surfaces, when the pore diameter is set around 0.1 mm. The experimental data on bubble formation showed a significant contribution of latent heat transport to the enhancement. A visualization study made with a transparent structured model suggested that the liquid suction into the tunnel is triggered by the bubble growth at active pores and subsequent evaporation inside the tunnel plays a vital role in driving the bubble formation cycle. This observation led to a conception of the dynamic model expounded in Part II.

Increasing miniaturization of microcircuits on chips of increasing size and new schemes of electrical connection, such as flip-chip bonding and surface mounting, are setting more demanding criteria regarding the thermal field within electronic equipment. While the search for a solution to meet a set of prescribed design criteria is becoming more complex, the body of available data needed to perform such a search is quite small. This article describes the two primary functions to be implemented by electronic heat transfer research: the definition of thermal design criteria and the establishment of a thermal packaging database. Examples of actual designs of packages are drawn from recent publications to illustrate the points of technical importance. The examples are packages of DRAM chips, flat-leaded packages of logic chips, and modules with dismountable heat sinks. These examples are used to address thermal stress problems, the problems of fin design, and thermal interface management, respectively. In the section on natural convection cooling, the effects of various factors on the uncertainties pertaining to heat transfer coefficient are assessed in light of the correlations proposed in the current literature. The section on forced convection cooling deals with the problem of heat transfer from an array of packages in a parallel-plate channel. The final section is devoted to the research topics of nucleate boiling heat transfer enhancement, from the surface of a small component, and microchannel cooling.

The purpose of this paper is to find an optimum surface geometry of vertical condenser tubes where condensation takes place on the outer surfaces. The guiding principle on optimum condensation performance is to make the thickness of condensate liquid on the surfaces as thin as possible. A vertical tube with longitudinally parallel tiny fins is preferable because condensate is made thinner over the widest possible region. According to an analysis, there are four controlling factors for the optimum fin; sharp leading edge, gradually changing curvature of fin surface from tip to the root, wide groove between fins to collect condensate and horizontal discs attached to the tube to remove condensate. The analytical result is checked by experiments using R-113. The optimum fin shape, fin pitch and spacing of discs are found by numerical calculations for R-113 and water.