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High-temperature microfluidic devices (such as gas chromatography microcolumns) have traditionally been fabricated using photolithography, etching, and wafer bonding which allow for precise microscale features but lack the ability to form complex 3D designs. Metal additive manufacturing could enable higher complexity microfluidic designs if reliable methods for fabrication are developed, but forming small negative features is challenging--especially in powder-based processes. In this paper, the formation of sealed metal microchannels was demonstrated using stainless-steel binder jetting with bronze infiltration. To create small negative features, bronze infiltrant must fill the porous part produced by binder jetting without filling the negative features. This was achieved through sacrificial powder infiltration (SPI), wherein sacrificial powder reservoirs (pore size ~60 µm) are used to control infiltrant pressure. With this pressure control, the infiltrant selectively filled the small pores between particles in the printed part (pore size ~3 µm) while leaving printed microchannels (700 µm and 930 µm) empty. To develop the SPI method, a pore filling study was performed in this stainless-steel/bronze system with 370 µm, 650 µm, and 930 µm microchannel segments. This study enabled SPI process design on these length scales by determining variations in pore filling across a sample and preferential filling between different sized pores. [ABSTRACT FROM AUTHOR]

A method to passively align bonded components without direct mechanical contact has been developed. This method uses the pressure field generated by the squeeze flow between the parts during the bonding process to increase the parallelism of planar components. A computational fluid dynamic (CFD) model has been developed to study the squeeze flow phenomenon and to determine generated efforts. Based on these calculations, an assembly stage standing on a flexure pinned linkage has been developed. This assembly stage had two purposes. The first was to show the possibility of passive mechanical alignment using a squeeze flow. The second was to measure efforts to confirm the CFD model. These measurements have led to a refined CFD model taking into account the non-Newtonian behavior of the fluid at high shear rates. This technique was initially developed for the assembly of a fiber-optic-to-silicon-chip-interface. Other potential applications could be wafer bonding, bonding of multiple wafer stacks, or 3D integrated circuits. [ABSTRACT FROM AUTHOR]

In this paper, we present the design of a passive test chip with thermal test structures in the Metal 1 layer of the back-end of line (BEOL) for the experimental thermal characterization of the intertier thermal resistance of wafer-pairs fabricated by three-dimensional (3D) hybrid Cu/dielectric wafer-to-wafer (W2W) bonding. The thermal test structures include heater elements and temperature sensors. The steady-state or transient measurement data are combined with a modeling study to extract the thermal resistance of the bonded interface for the fabricated bonded wafer pair. The extracted thermal resistance of the die-die interface created by hybrid wafer-to-wafer bonding is compared to literature data for die-to-die (D2D) or die-to-wafer (D2W) stacking with microbumps. The low thermal resistance of the thin bonded dielectric interface indicates that hybrid Cu/dielectric bonding is a promising technology to create 3D chip stacks with a low thermal die-to-die resistance. [ABSTRACT FROM AUTHOR]

3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC integration. They are different and in general the through-silicon via (TSV) separates 3D IC packaging from 3D Si/IC integrations since the latter two use TSV but 3D IC packaging does not. 3D Si integration and 3D IC integration are different. 3D IC integration stacks up the thin chips with TSV and microbump, while 3D Si integration stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart of 3D Si/IC integrations and is the focus of this investigation. Also, the state-of-the-art, challenge, and trend of 3D integration will be presented and examined. Furthermore, supply chain readiness for high volume manufacturing (HVM) of TSVs is discussed. [ABSTRACT FROM AUTHOR]