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A hysteresis loop of minority carrier lifetime vs voltage is found in polystyrenesulfonate (PSS)/Si organic-inorganic hybrid heterojunctions, implying an interfacial memory effect. Capacitance-voltage and conductance-voltage hysteresis loops are observed and reveal a memory window. A switchable interface state, which can be controlled by charge transfer based on an electrochemical oxidation/deoxidation process, is suggested to be responsible for this hysteresis effect. We perform first-principle total-energy calculations on the influence of external electric fields and electrons or holes, which are injected into interface states on the adsorption energy of PSS on Si. It is demonstrated that the dependence of the interface adsorption energy difference on the electric field is the origin of this two-state switching. These results offer a concept of organic-inorganic hybrid interface memory being optically or electrically readable, low-cost, and compatible with the flexible organic electronics. [ABSTRACT FROM AUTHOR]

Light-induced degradation has been identified to be a critical issue for most silicon-based solar cell technologies. This study presents an observation of an opposite light-induced enhancement (LIE) effect in photovoltaic performance in poly(3,4-ethylthiophene):polystyrenesulfonate/n-Si organicinorganic hybrid solar cells. The reduced density of interface states under light soaking (LS) is found to be responsible for the LIE of the hybrid solar cells. An increased minor carrier lifetime under LS and a switchable photoluminescence intensity while applying a voltage bias are observed, providing evidence for the underlying physical mechanism [ABSTRACT FROM AUTHOR]

The use of polystyrenesulfonate (PSS) thin films in a high-quality passivation scheme involving the suppression of minority carrier recombination at the silicon surface is presented. PSS has been used as a dispersant for aqueous poly-3,4-ethylenedioxythiophene. In this work, PSS is coated as a form of thin film on a Si surface. A millisecond level minority carrier lifetime on a high resistivity Si wafer is obtained. The film thickness, oxygen content, and relative humidity are found to be important factors affecting the passivation quality. While applied to low resistivity silicon wafers, which are widely used for photovoltaic cell fabrication, this scheme yields relatively shorter lifetime, for example, 2.40 ms on n-type and 2.05 ms on p-type wafers with a resistivity of 1-5 Ω·cm. However, these lifetimes are still high enough to obtain high implied open circuit voltages (Voc) of 708mV and 697mV for n-type and p-type wafers, respectively. The formation of oxides at the PSS/Si interface is suggested to be responsible for the passivation mechanism. [ABSTRACT FROM AUTHOR]