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Because of the exponential increase of sampling rate, time-interleaved analog-to-digital converter (TIADC) has a fast growth in the high-speed applications. However, the channel mismatch error is a serious challenge for the performance of TIADC. In this article, we address the timing skew mismatch error and propose a novel adaptive calibration method. The principle and operating process of the calibration algorithm are explained. To validate the proposed technique, we designed a four-channel TIADC-based digital oscilloscope with a sampling rate of 10 GS/s. Based on this instrumentation platform, (i) calibration algorithm was implemented by hardware; and (ii) a test platform consisting of advanced instruments and tools was setup to testify the effect and robustness of proposed algorithm. Moreover, the technical details of instrumentation are described for the first time. The experimental results show that the calibration algorithm significantly suppresses the distortions due to timing skew mismatch error. The TIADC-based instrumentation achieves spurious-free dynamic range of 52.48 dB and effective number of bits of 5.83 bit, respectively. Besides, the complexity of the proposed algorithm is compared and discussed. [ABSTRACT FROM AUTHOR]

The main factors that enable capture of complex and transient signals in real-time are improved sampling rates and processing speeds. The time-interleaved architecture is an effective method that allows systems to break through the speed bottleneck of single analog-to-digital converters (ADCs) and go beyond the state-of-the-art process technology limit. However, the performance of the acquisition system may be reduced because of the offset, gain, and time mismatch errors that occur in time-interleaved ADC systems. To correct these errors, this paper first proposes a self-adaptive correction algorithm and then introduces real-time solutions for this algorithm. Finally, the proposed calibration method is implemented in a digital phosphor oscilloscope. Simulations and experimental testing indicate that this system shows good real-time performance and provides a high dynamic performance with an effective number of bits of 7.3 bits and a signal-to-noise ratio of 45.5574 dB. [ABSTRACT FROM AUTHOR]

The wideband signal transceiver module forms the core component of the radar signal target simulator and the key module in measuring the Doppler shift. In this paper, we present a design for a miniaturized wideband signal transceiver module based on a PXIe bus, with an operating frequency range of 65 MHz–3 GHz, an instantaneous measurement bandwidth of 800 MHz on a standard 3U (where 1U = 4.445 cm) board with three slots. The module adopts a zero intermediate frequency transceiver, and the baseband uses two analog to digital converters, a field programmable gate array, and two digital to analog converters as the core hardware architecture. The module combines key technologies including variable-frequency local oscillator synthesis, radio-frequency broadband signal conditioning, and high-speed high-resolution baseband signal acquisition and generation. This paper describes a novel design for the Doppler shift function. Considering the limited size and volume of the module, Doppler shift technology combining a complex signal and a real signal was adopted to achieve full band coverage with an operating frequency range of 65 MHz–3 GHz. We verified that this module could generate the Doppler shift in the frequency band from −400 Hz to 400 Hz in steps of 2 Hz and with an error of ±2 Hz. [ABSTRACT FROM AUTHOR]

Publisher's Note: "An adaptive calibration technique of timing skew mismatch in time-interleaved analog-to-digital converters" [Rev. Sci. Instrum. The initially-published version incorrectly identified the university of first affiliation, the "University of Electronic Science and Technology of China", as the "University of Science and Technology of China", which is a different institution. All online versions of the article were corrected on 21 November 2019. [Extracted from the article]