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Stacking of two-dimensional electron gases (2DEGs) obtained by δ-doping of Ge and patterned by scanning probe lithography is a promising approach to realize ultrascaled 3D epitaxial circuits, where multiple layers of active electronic components are integrated both vertically and horizontally. We use atom probe tomography and magnetotransport to correlate the real space 3D atomic distribution of dopants in the crystal with the quantum correction to the conductivity observed at low temperatures, probing if closely stacked δ-layers in Ge behave as independent 2DEGs. We find that at a separation of 9 nm the stacked-2DEGs, while interacting, still maintain their individuality in terms of electron transport and show long phase coherence lengths (∼220 nm). Strong vertical electron confinement is crucial to this finding, resulting in an interlayer scattering time much longer (∼1000 ×) than the scattering time within the dopant plane. [ABSTRACT FROM AUTHOR]

The small footprint of semiconductor qubits is favorable for scalable quantum computing. However, their size also makes them sensitive to their local environment and variations in the gate structure. Currently, each device requires tailored gate voltages to confine a single charge per quantum dot, clearly challenging scalability. Here, we tune these gate voltages and equalize them solely through the temporary application of stress voltages. In a double quantum dot, we reach a stable (1,1) charge state at identical and predetermined plunger gate voltage and for various interdot couplings. Applying our findings, we tune a 2 × 2 quadruple quantum dot such that the (1,1,1,1) charge state is reached when all plunger gates are set to 1 V. The ability to define required gate voltages may relax requirements on control electronics and operations for spin qubit devices, providing means to advance quantum hardware.

Highly uniform quantum systems are essential for the practical implementation of scalable quantum processors. While quantum dot spin qubits based on semiconductor technology are a promising platform for large-scale quantum computing, their small size makes them particularly sensitive to their local environment. Here, we present a method to electrically obtain a high degree of uniformity in the intrinsic potential landscape using hysteretic shifts of the gate voltage characteristics. We demonstrate the tuning of pinch-off voltages in quantum dot devices over hundreds of millivolts that then remain stable at least for hours. Applying our method, we homogenize the pinch-off voltages of the plunger gates in a linear array for four quantum dots, reducing the spread in pinch-off voltages by one order of magnitude. This work provides a new tool for the tuning of quantum dot devices and offers new perspectives for the implementation of scalable spin qubit arrays.

A strained Ge quantum well, grown on a SiGe/Si virtual substrate and hosting two electrostatically defined hole spin qubits, is nondestructively investigated by synchrotron-based scanning X-ray diffraction microscopy to determine all its Bravais lattice parameters. This allows rendering the three-dimensional spatial dependence of the six strain tensor components with a lateral resolution of approximately 50 nm. Two different spatial scales governing the strain field fluctuations in proximity of the qubits are observed at <100 nm and >1 μm, respectively. The short-ranged fluctuations have a typical bandwidth of 2 × 10 -4 and can be quantitatively linked to the compressive stressing action of the metal electrodes defining the qubits. By finite element mechanical simulations, it is estimated that this strain fluctuation is increased up to 6 × 10 -4 at cryogenic temperature. The longer-ranged fluctuations are of the 10 -3 order and are associated with misfit dislocations in the plastically relaxed virtual substrate. From this, energy variations of the light and heavy-hole energy maxima of the order of several 100 μeV and 1 meV are calculated for electrodes and dislocations, respectively. These insights over material-related inhomogeneities may feed into further modeling for optimization and design of large-scale quantum processors manufactured using the mainstream Si-based microelectronics technology.

Topological superconductivity can be engineered in semiconductors with strong spin-orbit interaction coupled to a superconductor. Experimental advances in this field have often been triggered by the development of new hybrid material systems. Among these, two-dimensional electron gases (2DEGs) are of particular interest due to their inherent design flexibility and scalability. Here, we discuss results on a 2D platform based on a ternary 2DEG (InSbAs) coupled to in situ grown aluminum. The spin-orbit coupling in these 2DEGs can be tuned with the As concentration, reaching values up to 400 meV Å, thus exceeding typical values measured in its binary constituents. In addition to a large Landé g-factor of ∼55 (comparable to that of InSb), we show that the clean superconductor-semiconductor interface leads to a hard induced superconducting gap. Using this new platform, we demonstrate the basic operation of phase-controllable Josephson junctions, superconducting islands, and quasi-1D systems, prototypical device geometries used to study Majorana zero modes.

Hybrid superconductor-semiconductor structures attract increasing attention owing to a variety of potential applications in quantum computing devices. They can serve the realization of topological superconducting systems as well as gate-tunable superconducting quantum bits. Here, we combine a SiGe/Ge/SiGe quantum-well heterostructure hosting high-mobility two-dimensional holes and aluminum superconducting leads to realize prototypical hybrid devices, such as Josephson field-effect transistors (JoFETs) and superconducting quantum interference devices (SQUIDs). We observe gate-controlled supercurrent transport with Ge channels as long as one micrometer and estimate the induced superconducting gap from tunnel spectroscopy measurements. Transmission electron microscopy reveals the diffusion of Ge into the Al contacts, whereas no Al is detected in the Ge channel.

The achievement of controlled high n-type doping in Ge will enable the fabrication of a number of innovative nanoelectronic and photonic devices. In this work, we present a combined scanning tunneling microscopy, secondary ions mass spectrometry, and magnetotransport study to understand the atomistic doping process of Ge by P2 molecules. Harnessing the one-dimer footprint of P2 molecules on the Ge(001) surface, we achieved the incorporation of a full P monolayer in Ge using a relatively low process temperature. The consequent formation of P-P dimers, however, limits electrical activation above a critical donor density corresponding to P-P spacing of less than a single dimer row. With this insight, tuning of doping parameters allows us to repeatedly stack such 2D P layers to achieve 3D electron densities up to ∼2 × 10(20) cm(-3).

Low resistivity, near-surface doping in silicon represents a formidable challenge for both the microelectronics industry and future quantum electronic devices. Here we employ an ultra-high vacuum strategy to create highly abrupt doping profiles in silicon, which we characterize in situ using a four point probe scanning tunnelling microscope. Using a small molecule gaseous dopant source (PH3) which densely packs on a reconstructed silicon surface, followed by encapsulation in epitaxial silicon, we form highly conductive dopant sheets with subnanometer control of the depth profiles. This approach allows us to test the limits of ultra-shallow junction formation, with room temperature resistivities of 780 Ω/□ at an encapsulation depth of 4.3 nm, increasing to 23 kΩ/□ at an encapsulation depth of only 0.5 nm. We show that this depth-dependent resistivity can be accounted for by a combination of dopant segregation and surface scattering.

Despite the rapidly growing interest in Ge for ultrascaled classical transistors and innovative quantum devices, the field of Ge nanoelectronics is still in its infancy. One major hurdle has been electron confinement since fast dopant diffusion occurs when traditional Si CMOS fabrication processes are applied to Ge. We demonstrate a complete fabrication route for atomic-scale, donor-based devices in single-crystal Ge using a combination of scanning tunneling microscope lithography and high-quality crystal growth. The cornerstone of this fabrication process is an innovative lithographic procedure based on direct laser patterning of the semiconductor surface, allowing the gap between atomic-scale STM-patterned structures and the outside world to be bridged. Using this fabrication process, we show electron confinement in a 5 nm wide phosphorus-doped nanowire in single-crystal Ge. At cryogenic temperatures, Ohmic behavior is observed and a low planar resistivity of 8.3 kΩ/□ is measured.