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We investigate differential evolution optimization to fit Rutherford backscattering data. The algorithm helps to find, with very high precision, the sample composition profile that best fits the experimental spectra. The capabilities of the algorithm are first demonstrated with the analysis of synthetic Rutherford backscattering spectra. The use of synthetic spectra highlights the achievable precision, through which it becomes possible to differentiate between the counting statistical uncertainty of the spectra and the fitting error. Finally, the capability of the algorithm to analyze large sets of experimental spectra is demonstrated with the analysis of the position-dependent composition of a Sr[Formula: see text]Ti[Formula: see text]O[Formula: see text] layer on a 200 mm silicon wafer. It is shown that the counting statistical uncertainty as well as the fitting error can be determined, and the reported total analysis uncertainty must cover both.

Two-dimensional transition metal dichalcogenide (TMD) semiconductors have risen as an important material class for novel nanoelectronic applications. Molybdenum disulfide (MoS2) is the most representative TMD compound due to its superior stability and attractive properties for (opto-) electronic devices. However, the synthesis of single-crystalline and functional MoS2 across large-area substrates remains crucial for its successful integration in semiconductor industry platforms. Therefore, this work focuses on the study of MoS2 epitaxy via two well-established industry-compatible synthesis methods, promising for the large-area and single-crystalline integration of van der Waals (vdW) materials. These methods are molecular beam epitaxy (MBE) and metalorganic vapor phase epitaxy (MOVPE) and have studied MoS2 quasi-vdW heteroepitaxy on reconstructed sapphire substrates and MoS2 vdW homoepitaxy on exfoliated MoS2 flakes. By examining the MoS2 structural properties using diffraction and spectroscopy techniques, the epitaxial relation and crystal quality are assessed, which reveals insights into the prevalence of inter- and intragrain defects such as grain boundaries and sulfur vacancies. The MBE method yields superior epitaxial MoS2 registry on both sapphire and MoS2 surfaces as compared to MOVPE, although inferior defectivity arises from the typical lower MBE growth temperature and chalcogen partial pressure. Moreover, both synthesis methods generate high densities of twinned MoS2 grain boundaries, which hamper defect-free integration. As a result, this challenging integration might become an important bottleneck for industrial TMD-based applications with a low tolerance for material defects.

© 2018 Author(s). In0.53Ga0.47As p + n diodes with different densities of extended defects have been analyzed by detailed structural and electrical characterization. The defects have been introduced during Metal-Organic Vapor Phase Epitaxy (MOVPE) growth by using a lattice-mismatched layer on a semi-insulating InP or GaAs substrate. The residual strain and indium content in the n-type In0.53Ga0.47As layer have been determined by high-resolution X-ray diffraction, showing nearly zero strain and a fixed indium ratio of 0.53. The deep levels in the layer have been characterized by Deep Level Transient Spectroscopy. The mean value of electron traps at 0.17 ± 0.03 eV below the conduction band minimum EC is assigned to the "localized" states of α 60° misfit dislocations; another broad electron trap with mean activation energies between EC- 0.17 ± 0.01 and 0.39 ± 0.04 eV, is identified as threading dislocation segments with "band-like" states. A high variation of the pre-exponential factor KT by 7 orders of magnitude is found for the latter when changing the filling pulse time, which can be explained by the coexistence of acceptor-like and donor-like states in the core of split dislocations in III-V materials. Furthermore, two hole traps at EV+ 0.42 ± 0.01 and EV+ 0.26 ± 0.13 eV are related to the double acceptor of the Ga(In) vacancy (VGa/In3-/2-) and 60° β misfit dislocations, respectively. Finally, the dislocation climbing mechanism and the evolution of the antisite defects AsGa/In are discussed for n-type In0.53Ga0.47As. ispartof: JOURNAL OF APPLIED PHYSICS vol:124 issue:16 status: published

Vertical InAs nanowires (NWs) grown on a Si substrate are promising building-blocks for next generation vertical gate-all-around transistor fabrication. We investigate the initial stage of InAs NW selective area epitaxy (SAE) on a patterned Si (111) substrate with a focus on the interfacial structures. The direct epitaxy of InAs NWs on a clean Si (111) surface is found to be challenging. The yield of vertical InAs NWs is low, as the SAE is accompanied by high proportions of empty holes, inclined NWs, and irregular blocks. In contrast, it is improved when the NW contains gallium, and the yield of vertical InxGa1-xAs NWs increased with higher Ga content. Meanwhile, unintentional Ga surface contamination on a patterned Si substrate induces high yield vertical InAs NW SAE, which is attributed to a GaAs-like seeding layer formed at the InAs/Si interface. The role of Ga played in the III-V NW nucleation on Si is further discussed. It stabilizes the B-polarity on a non-polar Si (111) surface and enhances the nuc...

We present in this paper the use of Gas Source Molecular Beam Epitaxy for the large-scale growth of transition metal dichalcogenides. Fiber-textured MoS2 co-deposited thin films (down to 1 MLs) are grown on commercially 200 mm wafer size templates where MX2 crystalline layers are achieved at temperatures ranging from RT to 550 °C. Raman Spectroscopy and photoluminescence measurements along with X-Ray Photoelectron Spectroscopy show that a low growth rate is essential for complete Mo sulfurization during MoS2 co-deposition. Finally, cross-section Transmission Electron Microscopy investigations are discussed to highlight the influence of SiO2 and Al2O3 used surfaces on MoS2 deposition.

In this work, we present a systematic study of the effect of the stoichiometry of BaTiO3 (BTO) films grown on the Ge(001) substrate by molecular-beam-epitaxy using different characterization methods relying on beam diffraction, including reflection high-energy electron diffraction (RHEED), X-ray diffraction (XRD), and selected-area electron diffraction in transmission electron microscopy. Surprisingly, over a wide range of [Ba]/[Ti] ratios, as measured by the Rutherford backscattering spectrometry, all the BTO layers exhibit the same epitaxial relationship < 100 > BTO(001)//< 110 > Ge(001) with the substrate, describing a 45 degrees lattice rotation of the BTO lattice with respect to the Ge lattice. However, varying the [Ba]/[Ti] ratio does change the diffraction behavior. From RHEED patterns, we can derive that excessive [Ba] and [Ti] generate twinning planes and a rougher surface in the non-stoichiometric BTO layers. XRD allows us to follow the evolution of the lattice constants as a function of the [Ba]/[Ti] ratio, providing an option for tuning the tetragonality of the BTO layer. In addition, we found that the intensity ratio of the 3 lowest-order Bragg peaks I-(001)/I-(002), I-(101)/I-(002), and I-(111)/I-(002) derived from omega - 2 theta scans characteristically depend on the BTO stoichiometry. To explain the relation between observed diffraction patterns and the stoichiometry of the BTO films, we propose a model based on diffraction theory explaining how excess [Ba] or [Ti] in the layer influences the diffraction response. Published by AIP Publishing.

© 2015 AIP Publishing LLC. Metrology for structural and electrical analyses at device level has been identified as one of the major challenges to be resolved for the sub-14 nm technology nodes. In these advanced nodes, new high mobility semiconductors, such as III-V compounds, are grown in narrow trenches on a Si substrate. Probing the nature of the defects, the defect density, and the role of processing steps on the surface of such structures are prime metrology requirements. In order to enable defect analysis on a (III-V) surface, a proper sample preparation for oxide removal is of primary importance. In this work, the effectiveness of different chemical cleanings and thermal annealing procedures is investigated on both blanket InP and oxide embedded InP trenches by means of scanning probe microscopy techniques. It is found that the most effective approach is a combination of an HCl-based chemical cleaning combined with a low-temperature thermal annealing leading to an oxide free surface with atomically flat areas. Scanning tunneling microscopy (STM) has been the preferred method for such investigations on blanket films due to its intrinsic sub-nm spatial resolution. However, its application on oxide embedded structures is non-trivial. To perform STM on the trenches of interest (generally

High quality GaAs is selectively grown in 40 nm width Shallow Trench Isolation patterned structures. The patterned wafers have a V-shape Si (111) surface obtained by Tetramethylammonium hydroxide etching. By employing a SiCoNi™ pre-epi clean and two-step growth procedure (low temperature buffer and high temperature main layer), defects are effectively confined at the trench bottom, leaving a dislocation-free GaAs layer at the upper part. The high crystal quality is confirmed by transmission electron microscopy. Scanning spreading resistance microscopy indicates a high resistance of GaAs. The process conditions and GaAs material quality are highly compatible with Si technology platform.

Spectroscopy of internal photoemission of electrons from Ge and Ge1−xSnx (x ≤ 0.08) alloys into amorphous Al2O3 is used to evaluate the energy of the semiconductor valence band top. It is found that in Ge and Ge1−xSnx the valence bands are aligned within the measurement accuracy (±0.05 eV) irrespective of the strain imposed on the semiconductor or by the kind of passivating inter-layer applied between the semiconductor and alumina. This indicates that the Ge1−xSnx-stressor approach may be useful for strain engineering in p-channel Ge metal-oxide-semiconductor transistors.

This study relates to the heteroepitaxy of InP on patterned Si substrates using the defect trapping technique. We carefully investigated the growth mechanism in shallow trench isolation trenches to optimize the nucleation layer. By comparing different recess engineering options: rounded-Ge versus V-grooved, we could show a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. The demonstration of III-V heteroepitaxy at scaled dimensions opens the possibility for new applications integrated on Silicon. ispartof: Journal of Applied Physics vol:115 issue:2 pages:023710-1 status: published

The evolution of (001) and (111) facets for the epitaxial growth inside submicron trenches is systematically studied in this report. The analysis with the method of “Lagrange multiplier” indicates the equilibrium crystal shape. In the case of non-equilibrium without external fluxes, we employed the “weighted mean curvature” method to mathematically model the inter-facet migration rate for two extreme kinetic cases: “surface diffusion limited” and “surface attachment/detachment limited.” Coupled with external supply of atoms, the self-limited behavior of facet size is theoretically predicted. Moreover, we find that the self-limited stable facet size in trenches of different widths has a specific relationship determined by the surface energy ratio, kinetic rate ratio, and isolated growth rate difference. The two limited cases could be discriminated according to the mathematical fitting of one exponent in this relationship based on the stable facet size in trenches of different widths. ispartof: Journal of Applied Physics vol:115 issue:2 pages:1-7 status: published

We use an improved AC conductance method and a modified Gray-Brown method to study fast interface traps and slow border traps in Ge-based MOS capacitors. The combined methods provide the corrected Fermi energy level (E) versus gate voltage (Vg) relationship, even in samples with high densities of traps that cause significant C-V distortion, the energy distribution of interface traps, their capture cross sections (σ), as well as slow border traps. A wide range of σ’s in p-type Ge is found, indicating that there is more than one type of interface trap near the Ge valence band edge. In contrast, a constant σ near the Ge conduction band edge is observed in n-type Ge. XPS results indicate that Ge suboxides near the interface are accountable for the detected slow border traps.

Tuning the desorption temperature of an As cap layer allows to achieve In0.53Ga0.47As(001) surfaces with (2 x 4) and (4 x 2) reconstructions which exhibit different chemical reactivity upon exposure in atmospheric pressure. Trimethyl-Al based atomic layer deposition of Al2O3 films on the two exposed surfaces causes a non-equivalent interface composition. This behavior is associated with a worse electrical quality of the interface with the exposed (4 x 2) In0.53Ga0.47As reconstruction. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3659688] We acknowledge grant from ARAMIS Project and M. Alia (MDM) for metal gate deposition

In this letter, we propose an atmospheric pressure-chemical vapor deposition technique to grow metastable GeSn epitaxial layers on Ge. We report the growth of defect free fully strained undoped and in-situ B doped GeSn layers on Ge substrates with Sit contents up to 8%. Those metastable layers stay fully strained after 30 min anneal in N-2 at 500 degrees C.; Ge-Sn interdiffusion is seen at 500 degrees C but not at lower temperature. B is 100% active in the in-situ GeSn:B layers up to a concentration of 1.7 x 10(19) cm(-3). GeSn:B provides slightly lower Hall hole mobility values than in pure p-type Ge especially for low B concentrations. (C) 2011 American Institute of Physics [doi.10.1063/1.3645620]

The efficiency of the ammonium sulfide vapor (ASV) treatment, as opposed to the wet treatment in the liquid ammonium sulfide solution, on the performance improvement of the In0.53Ga0.47As surface-channel as well as InP-capped buried-channel metal-oxide-semiconductor field-effect-transistors (MOSFET) was demonstrated for the first time. MOSFETs were fabricated with either HCl or ASV surface treatments prior to the gate oxide deposition. ASV treatment was found to be very efficient in boosting the drive current of the transistors compared to that of the HCl treatment. It was also found that the ASV treatment leads to a lower border trap density and slightly higher oxide/semiconductor interface defect density compared to that of the HCl treatment. X-ray photoelectron spectroscopy (XPS) studies of In0.53Ga0.47As native oxide regrowth after both surface treatments identified indium sub-oxides as a possible cause of the performance degradation of the HCl treated devices. Based on this work, ASV treatment could be an efficient solution to the passivation of III-V surfaces. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3638492] The authors acknowledge the European Commission for financial support in the DualLogic project no. 214579. Further, we thank the IMEC core partners within the IMEC’s Industrial Affiliation Program on Logic/Ge-III/V.

Experiments on internal photoemission of electrons from Si and TiNx into thin Al2O3 layers suggest that crystallization of amorphous Al2O3 to the cubic γ-Al2O3 is accompanied by only a ≈ 0.5 eV upshift of the conduction band bottom edge. As it is known that in transforming from the amorphous to the γ-phase, the bandgap of Al2O3 increases from 6.2 eV to 8.7 eV, more than 80% of this gap widening must occur at the VB side of the gap. The latter suggests that interaction between electron states of O anions plays the dominant role in the oxide gap widening.

We investigated the molecular beam deposition of Al2O3 on Ge0.95Sn0.05 surface with and without an ultra thin Ge cap layer in between. We first studied the atomic configuration of both Ge1−xSnx and Ge/Ge1−xSnx surfaces after deoxidation by reflection high-energy electron diffraction and resulted, respectively, in a c(4×2) and (2×1) surface reconstructions. After in situ deposition of an Al2O3 high-κ gate dielectric we evidenced using time-of-flight secondary ion mass spectroscopy analyses that Sn diffusion was at the origin of high leakage current densities in the Ge1−xSnx/Al2O3 gate stack. This damage could be avoided by inserting a thin 5-nm-thick Ge cap between the oxide and the Ge1−xSnx layer. Finally, metal-oxide-semiconductor capacitors on the Ge capped sample showed well-behaved capacitance-voltage (C-V) characteristics with interface trap density (Dit) in the range of 1012 eV−1 cm−2 in mid gap and higher close to the valence band edge.

The integration of high carrier mobility materials into future CMOS generations is presently being studied in order to increase drive current capability and to decrease power consumption in future generation CMOS devices. If III-V materials are the candidates of choice for n-type channel devices, antimonide-based semiconductors present high hole mobility and could be used for p-type channel devices. In this work we first demonstrate the heteroepitaxy of fully relaxed GaSb epilayers on InP(001) substrates. In a second part, the properties of the Al2O3/GaSb interface have been studied by in situ deposition of an Al2O3 high-kappa gate dielectric. The interface is abrupt without any substantial interfacial layer, and is characterized by high conduction and valence band offsets. Finally, MOS capacitors show well-behaved C-V with relatively low D-it along the bandgap, these results point out an efficient electrical passivation of the Al2O3/GaSb interface. (C) 2011 American Institute of Physics. [doi:10.1063/1.3569618] This work is part of the IMEC Industrial Affiliation Program and is supported by the European Commission’s project FP7-ICT-DUALLOGIC no. 214579, “Dual-Channel CMOS for (sub)-22nm High Performance Logic.” The authors would like to thank Th. Conard and A. Franquet for XPS characterizations, F. Paola and H. Bender for TEM analyses, and H. Costermans for the support of the MBE tool.