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Leakage power consumption is a large fraction of the total power consumption in contemporary VLSI designs. Since memories occupy a large portion of the total area of many high-performance ICs, it is crucial to reduce the leakage energy of memories. This problem is particularly aggravated for memories implemented in the 45nm technology node, since these processes exhibit significantly higher leakage power. For these memories, leakage is a significant problem not only from a power point of view, but also from a performance degradation standpoint. In this paper, we quantify this problem and provide a solution, using a 512KByte SRAM implemented in a 45nm bulk process as a design example. We show that implementing the SRAM as a monolithic memory results in increased delay as well as power. We illustrate a methodology to optimally reduce leakage power and improve performance in memories by splitting the memory array into word line groups (WLGs) which are selectively forward body biased when accessed. We present a derivation of optimal number of WLGs and the forward body bias voltage value, and show that our approach results in a 9:2% access time reduction, and a 53:4% reduction in power during a read operation. Our approach also achieves an 18% reduction in power during a write operation and a 69% leakage power improvement. The area overhead of our scheme is 7:2% compared to a monolithic memory.

Single event upsets (SEUs) are becoming increasingly problematic for both combinational and sequential circuits with device scaling, lower supply voltages and higher operating frequencies. To design radiation tolerant circuits efficiently, techniques are required to analyze the effects of a particle strike on a circuit early in the design flow and also to evaluate the circuit's resilience to SEU events. In this paper, we present an analytical model for SEU induced transients in combinational circuits. The pulse width of the voltage glitch due to an SEU event is a good measure of SEU robustness and our model efficiently computes it for any combinational gate. The experimental results demonstrate that our model is very accurate with a very low pulse width estimation error of 4% compared to SPICE. Our model gains its accuracy by using a non-linear transistor current model, and by considering the effect of tauB of the radiation induced current pulse. Our analytical model is very fast and accurate, and can therefore be easily incorporated in a design flow to implement SEU tolerant circuits.

In this paper, we present a pipelined Network of PLA based circuit design approach. Our approach can be used to realize an arbitrary logic circuit with an extremely high throughput and low latency. Using logic synthesis tools to decompose a logic circuit into this framework, and appropriately inserting "stutter" blocks to balance the logical depth of all paths in the decomposed circuit, we come up with a pipelined network of PLA netlist. We have demonstrated the effectiveness of the approach via SPICE simulations and layout generation experiments. Throughput, latency, and area are compared with competing approaches, demonstrating the power of this design style. We show that our approach has a 75% better throughput than the asynchronous micropipelining based technique, and a latency which is 63% that of the asynchronous scheme. Both techniques were implemented in a super-threshold fashion. We have also conducted Monte Carlo experiments to validate the approach under variations.

High Speed VLSI design utilizes heavy pipelining, resulting in a large number of flip-flops in the circuit. Hence there is a strong motivation to design fast, low power and area efficient flip-flops. In this paper, we present a pulsed flip-flop design based on a novel pulse generator circuit. Our design achieves significantly improved speed when compared to recent pulsed flip-flop design, as well as a traditional master-slave D flip-flop. Monte Carlo simulations demonstrate that our design is significantly more robust to variations than the other flip-flops. Our design consumes low power as well. Also we have performed the layout of our design and shown that our layout area is smaller than a traditional D flip-flop.

Integrated circuit manufacturing costs are increasing with decreasing device feature sizes, due to significant increases in mask costs. At the same time, systematic processing variations due to optical proximity effects are also increasing, making it harder to predict the circuit behavior with fidelity. Therefore, there is a need to implement designs using regular circuit structures. In this paper, we present a new structured ASIC approach which utilizes an array of 2-input NAND gates. Our NAND2 array based circuit implementation reduces manufacturing costs, and design turn-around times because different designs can share the same masks up to the poly layer. The regular layout structure of our NAND2 array also helps in reducing systematic variations. We compared the performance of our NAND2 array with the ASIC approach by implementing several benchmark circuits using both methods. The experimental results demonstrate that on average, our approach has a delay penalty of 40%, an area penalty of 12%, and a power increase of 7%, compared to an ASIC design approach. This is better than the previously reported structured ASIC approaches. We also performed lithographical simulations of the poly and metal masks of the designs implemented using our approach as well as the ASIC design approach. These lithographical simulation results demonstrate that our approach has lower errors on the poly and the Metal1 layers by 7% and 24% respectively, compared to the ASIC approach.

When a signal traverses on-chip voltage domains, a level shifter is required. Inverters can handle a high to low voltage shift with minimal leakage. For a low to high voltage level translation, inverters tend to consume a large amount of leakage power, and hence special circuits have been proposed for this type of translation. This paper reports a novel single-supply "true" (in the sense that it can handle a low to high, or high to low voltage level conversion) voltage level shifter, which can handle low-to-high and high-to-low voltage translation. Such a requirement arises in many modern ICs or systems-on-chip (SoCs). The use of single supply voltage reduces circuit complexity by eliminating the need for routing both supply voltages. The proposed circuit was extensively simulated in a 90 nm technology using SPICE. Simulation results demonstrate that the level shifter is able to perform voltage level shifting with low leakage for both low to high, as well as high to low voltage level translation. We have validated the correct operation of the proposed level shifter under process and temperature variations as well.

In this paper, we present a radiation-hardened digital design approach. This approach is based on the use of code word state preserving (CWSP) elements at each flip-flop of the design, and leaving the rest of the design unaltered. The CWSP element provides 100% SET protection for glitch widths up to min{Dmin/2, (Dmax - Delta)/2}, where Dmin and Dmax are the minimum and maximum circuit delay respectively and Delta is an extra delay associated with our SET protection circuit. The CWSP circuit has two inputs - the latch output signal and the same signal delayed by a quantity delta. In case an SET error is detected, then the current computation is repeated, using the correct output, which is generated later in the same clock period by the CWSP element. Unlike previous approaches, we use the CWSP element in a secondary path and the CWSP logic is designed to minimally impact the critical delay path of the design. The delay penalty of our approach (averaged over several designs) is less than 1%. Thus our technique is applicable for high-speed designs, where the additional delay associated with SET protection must be kept at a minimum.

The determination of metal wire dimensions and inter-layer dielectric thicknesses has become increasingly important in recent times, as wire delays have begun to dominate transistor delays. In this paper, we propose metrics to guide the determination of these dimensions, along with results which describe the efficacy of these metrics. The first metric, which we refer to as cross-bar bandwidth(CBB), compares different wiring configurations in terms ofthe resulting bandwidth they can support in a square of unitsize. The second metric, called power-adjusted cross-bar bandwidth (PCBB), measures the bandwidth of a square, while accounting for the power consumed by the interconnect in the square. The application of these metrics suggests that the traditional approach (of fabricating interconnect of the finest pitch possible) may be sub-optimal with respect to either metric that we present. We have conducted our experiments for layers METAL1 through METAL4, although the approach is general and can be applied to the problem of determining interconnect dimensions for any layer. Without considering driver resistance, our approach yields up to 16% improvement in CBB and 19% improvement in PCBB. When drivers are modeled, the improvements are even greater.

This paper presents a design flow that optimizes a standard cell based circuit for performance by implementing critical paths in a Programmable Logic Array (PLA). Given a standard-cell based circuit as input, our approach iteratively extracts critical paths from this circuit, which are then implemented using a PLA circuit. PLAs are a good candidate for such an approach, since they exhibit a gradual increase in delay as additional vectors are added. In subsequent iterations, these critical paths are treated as don't cares, allowing the standard cell based design to be simplified after each iteration. The final design consists of a portion which is implemented using a PLA, and another portion which is implemented using standard cells. We demonstrate that on average, our approach can achieve about 22.5% improvement in the SPICE based delay of a design, along with a placed-and-routed area improvement of 11%.