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Circuit benchmarks for VLSI physical design have been growing in size and complexity, helping the industry tackle new problems and find new approaches. In this paper, we take a look back at how benchmarking efforts have shaped the research community, consider trade-offs that have been made, and speculate on what may come next.

Interconnect spacing is getting increasingly smaller in advanced technology nodes, which adversely increases the capacitive coupling of adjacent interconnect wires. It makes crosstalk a significant contributor to signal integrity and timing, and it is now imperative to prevent crosstalk-induced noise and delay issues in the earlier stages of VLSI design flow. Nonetheless, since the crosstalk effect depends primarily on the switching of neighboring nets, accurate crosstalk evaluation is only viable at the late stages of design flow with routing information available, e.g., after detailed routing. There have also been previous efforts in early-stage crosstalk prediction, but they mostly rely on time-expensive trial routing. In this work, we propose a machine learning-based routing-free crosstalk prediction framework. Given a placement, we identify routing and net topology-related features, along with electrical and logical features, which affect crosstalk-induced noise and delay. We then employ machine learning techniques to train the crosstalk prediction models, which can be used to identify crosstalk-critical nets in placement stages. Experimental results demonstrate that the proposed method can instantly classify more than 70% of crosstalk-critical nets after placement with a false-positive rate of less than 2%.

We describe the RDF-2020 release of the IEEE CEDA DATC Robust Design Flow (RDF). RDF-2020 extends the previous four years of DATC efforts to (i) preserve and integrate leading research codes, including from past academic contests, and (ii) provide a foundation and backplane for academic research in the RTL-to-GDS IC implementation arena. Implementation and analysis flows have been enhanced by the addition of steps including multi-bit flip-flop clustering, parasitic extraction and antenna checking, as well as a recent contest-winning global router. RDF-2020 also opens a new "Calibrations" direction to support academic research on key analyses such as extraction and timing. An open-source physical design database with Tcl/Python/C++ APIs, a flow integration into a single scriptable application, and support for the newly-opened SKY130 manufacturable PDK, are also new this year. Our paper closes with a discussion of potential future directions for the RDF effort.

In this paper, we present DATC Robust Design Flow (RDF) from logic synthesis to detailed routing. We further include detailed placement and detailed routing tools based on recent EDA research contests. We also demonstrate RDF in a scalable cloud infrastructure. Design methodology and cross-stage optimization research can be conducted via RDF.

The layout of standard cells is very dense these days, so some pins are hard to get access to. This is in particular true in complex cells with many pins (e.g. AOI) and in the layout where many of those cells are densely packed without much whitespace. We redesign those complex cells, so a library now contains both original cell and its new version with easier pin access; a systematic method is proposed to pick candidate cells for redesign and to dictate how redesign should be performed. We also introduce a measure of inaccessibility of pins in a cell, named IOC. Placement optimization is performed, which uses IOC to determine which cells should be replaced by its redesigned version and how whitespace should be redistributed. Experiments with 12 test circuits indicate that the number of routing errors (after the initial placement) is reduced by 82% on average, and the subsequent detailed routing takes 72% less runtime.

Line-end cuts are employed to enable 1D gridded designs in self-aligned double patterning (SADP) process. Due to the minimum spacing constraints between adjacent cuts, cut optimization is important component. However, it brings a new challenge to redundant via (RV) insertion. As the cuts for RVs are not taken into account during line-end cut optimization, inserting some RVs may cause coloring conflicts or design rule violations. In this paper, we address a combined RV insertion and cut optimization problem. Given a via layout, the proposed approach optimizes the cuts in upper and lower metal layers, which are connected through a via, while RV candidate positions are considered. Only the RV candidates that do not incur coloring conflicts and design rule violations are chosen. Our experiments indicate that only 55.3% of vias receive RVs when cut optimization and RV insertion are performed separately; corresponding number increases to 86.4% when our approach is applied.

This paper proposes a powerful new technique called "OWARU"1 that re-places and re-sizes multiple gates simultaneously to improve the most critical paths of a design. In essence, it is an incremental timing-driven placement technique integrated with gate sizing optimization that runs in conjunction with static timing analysis to guarantee a WYSIWYG 2 property. The OWARU technique offers several key advantages over previous techniques such as geometrical path straightening via the Bezier-curve algorithm, free space awareness to guarantee a legal placement solution, and an accurate true timing mode. The Bezier-curve geometric smoothing algorithm is extended with new anchor placement techniques to further improve the path placement. Free space aware placement algorithm is further enhanced with multiple gate optimization. The preliminary results are promising. We applied the OWARU technique at the end of industrial strength physical synthesis optimization on high performance microprocessor designs. The technique was extremely effective in improving the most critical path of the tested designs. On timing critical paths that were not fully closed from the previous physical synthesis optimization, the WS (worst slack) is improved by 5.3% of the total clock period and the TNS (total negative slack) improved by 91.3% on average.

Recently, there have been a slew of design automation contests and released benchmarks. ISPD place & route contests, DAC placement contests, timing analysis contests at TAU and CAD contests at ICCAD are good examples in the past and more of new contests are planned in the upcoming conferences. These are interesting and important events that stimulate the research of the target problems and advance the cutting edge technologies. Nevertheless, most contests focus only on the point tool problems instead of addressing the design flow or co-optimization among design tools. OpenDesign Flow Database platform is developed to direct attentions to the overall design flow from logic synthesis to physical design optimization [1]. The goals are to provide an academic reference design flow based on past CAD contest results, the database for design benchmarks and point tool libraries, and standard design input/output formats to build a customized design flow by composing point tool libraries.