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This paper proposes a wideband 0.4-2 GHz cascode common-gate LNA that can be used as a building block for a noise canceling topology (which entails its noise to be canceled at the output node). The design strategy is to set the operating point by analyzing the third order coefficient $(\alpha_{3})$ of the output current and the output voltage, which is designed using a load composed by a diode-connected PMOS transistor and a resistor in parallel. This operating point allows a reasonable $V_{GS}$ spread, maintaining a high IIP3 which implies a low IIP3 sensitivity to process variability. The design strategy also achieves a current consumption under 1 mA and, depending on the technology node $V_{DD}$ (CMOS 130 nm in this case), it can consume under 1 mW of power. This makes the wideband LNA suitable for IoT applications. Monte Carlo simulations have been carried out to demonstrate the operating region sensitivity to variability and achieves a result of worst case $IIP3_{\mu}=+0.2\ \mathrm{dBm}$ with $\sigma=0.8\ \mathrm{dBm}$ (@2GHz) up to a nominal 2.75 dBm @900 MHz, $S_{11} (canceled by virtue of its topology), a voltage gain of 11.6-14.6 dB ( $S_{21}=6.4-9.4\ \mathrm{dB}$ with a buffer to $50\ \Omega$ ), and consuming just 1.19 mW from a 1.2 V supply.

Internet of Things (IoT) is a topic of growing interest and intensive research in industry, technological centers and academy, where data communication is one of its most relevant aspects. Since IoT is an open field for new applications, it does not have yet a standard communication protocol. This paper presents the system level design of a Wi-Fi receiver supporting the novel low power standard IEEE 802.11ah with focus on IoT applications. Theoretical performance analysis as well as system level design strategies are presented. Individual blocks of the receiver chain are specified as a condition for future circuit-level design. Simulation results validate the proposed system specifications attending the 802.11ah standard. The presented receiver provides 80.5dB maximum gain, 9 dB minimum noise figure and 69.4 dB of dynamic range. Those performance parameters lead to -99.4 dBm sensitivity, 21 dB and 51 dB for adjacent and non-adjacent maximum channel rejection.

This work presents a 2-decades wideband (15.5 MHz–1.55 GHz) low-noise amplifier (LNA) circuit. As its wideband range extends from HF to UHF, it includes, among others, the ISM bands (27.12 MHz, 40.7MHz, 434.79 MHz, 928 MHz), the GSM850 and GSM900 bands, and IEEE 802.22 WRAN bands (54 MHz–862 MHz). The proposed circuit operates also as a balun (single-ended input — differencial output) and its layout presents a very small area, an important savings resulting from this inductorless design for the LNA. An auxiliary amplifier was introduced so that a high gain and a high IIP3 can be achieved with low Noise Figure (NF). The linearity was improved using a distortion cancellation strategy and the NF was improved through a noise canceling technique. The amplifier was implemented in a 130 nm CMOS process, using a PDK from Silterra foundry, in a compact 77μm × 54μm core area. Simulations including post-layout parasitics, bondwire, ESD protection and PAD input parasitics resulted (over the entire band) in a voltage gain of 20.8–24.9 dB, a noise figure (NF) of 2.7–3.7 dB, an input power reflection coefficient Sn < −11.4 dB, an input third-order intercept point (IIP3) = −0.4 dBm (@750MHz), and a power consumption of 10.4 mW under 1.2 V supply. This balun LNA shows a worst case gain imbalance between outputs of 1.2 dB and very low sensitivity to temperature variations for gain, NF and Sn in the range of 0 to 85°C.

This work presents a high PSRR nano-watt resistorless thresh old voltage (VTo) monitor circuit that can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications such as fabrication process monitoring and verification. In this circuit design the MOS transistors operate in subthreshold and near-threshold regimes, the circuit analysis is based on a current-voltage relationship derived from a continuous physical MOSFET model, valid from weak to strong inversion. The bias condition is established from the equilibrium between two self-cascode cells operating at different inversion levels, and the high PSRR results from a high gain feedback path. The circuit is MOSFET-only, and can be implemented in any standard digital CMOS process. Post-layout simulations show that it operates with less than 1 V of power supply, consuming only tens of nW, and resulting in a VT0 error lower than 1%, when compared to its modeling value, for a −40 to +125°C temperature range. A very high rejection to VDD variation is achieved in this design, with PSRR lower than −63.9 dB at 100 Hz, and a line sensitivity lower than 252 ppm/V was found for a supply range from 1 V to 3 V. Monte-Carlo simulations are presented to evaluate the fabrication variability sensitivity, presenting a maximum error of 4% for a 3a spread range. The circuit area is very small, around 0.0047 mm2 including the start-up stage.

This work presents a self-biased MOSFET threshold voltage V T0 extractor circuit. Its working principle is based on a current-voltage relationship derived from a continuous physical model. The model is valid for any operating condition, from weak to strong inversion, and under triode or saturation regimes. The circuit is MOSFET-only (can be implemented in any standard digital process), and it operates with a power supply of less than 1 V, consuming tenths of nW. Post-layout simulation results show that the extracted V T0 has an error inferior to 1.3%, when compared to the theoretical value, for a −40 to 125°C temperature range. We present variability results from Monte Carlo simulations that support the extracting behavior of the circuit with good accuracy. The occupied silicon area is 0.0076 mm2 in a 0.13µm CMOS process.

This paper presents a high-linearity and large output swing instrumentation amplifier for portable multichannel biomedical applications. It is composed of a fully differential two-stage CMOS amplifier in which a feedback provides stable signal gain that can be adjusted from 25 to 100 V/V. Additionally, a pseudo-resistive feedback combined with an appropriate input capacitive coupling provides a high-pass behavior, presenting a −3 dB cut-off frequency lower than 120 mHz. The amplifier is fully integrated in a 130 nm CMOS process, using only 0.1 mm2 of silicon area, including large matched capacitor banks. Its power consumption is 31.3 µW under a 1.5 V supply. The pre-amplifier gain reaches less than 0.02 % of THD (total harmonic distortion) for an output swing of 2 Vpp in post-layout simulations. The total input-referred noise estimated from simulations is 1.93 µVrms inside the 0.5 Hz to 500 Hz frequency range.

A MOSFET-only sub-bandgap voltage reference at less than 50 nW and with very low temperature coefficient is introduced. It consists of a threshold voltage extractor circuit and a proportional to absolute temperature voltage generator, using no resistors. The behavior of the circuit is analytically described, a design methodology is proposed and simulation results for a 0.13 µm CMOS process are presented. It allows a reference voltage below the bandgap, 625 mV in this design example, achieving a temperature coefficient of 2.3 ppm/°C for the -40 to 125 °C temperature range. The circuit consumes 40 nW at 27°C and under 1.2 V supply, being the implemented silicon area 0.0099 mm².

This paper describes a test circuit for intensive characterization of MOS transistors mismatch. It aggregates analog switches, a shift register and a reference circuit, as well as the matrix of 1296 transistors to be tested. This circuit was integrated in a 0.35 mm bulk technology, and was designed to give experimental support for our MOSFET mismatch model. The test chip was characterized over a wide range of operation conditions, from weak to strong inversion, from linear to saturation region, allowing the analysis of MOSFET mismatch from bias, process and geometric parameters.

Electron device matching has been a key factor on the performance of today's analog or even digital electronic circuits. This paper presents a study of drain current matching in MOS transistors. CMOS test structures were designed and fabricated as a way to develop an extensive experimental work, where current mismatch was measured under a wide range of bias conditions. A model for MOS transistor mismatch was also developed, using the carrier number fluctuation theory to account for the effects of local doping fluctuations. This model shows a good fitting with measurements over a wide range of operation conditions, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters.